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v5.0
40MX and 42MX FPGA Families
Fe a t ur es
High C apaci t y
* * * * * * * * * *
Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 202 User-Programmable I/O Pins 5.6 ns Clock-to-Out 250 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode
* Commercial, Military Temperature and MIL-STD-883 Ceramic Packages * QML Certification * Ceramic Devices Available to DSCC SMD
E ase of Int egr at io n
* Mixed Voltage Operation (5.0V or 3.3V I/O) * Synthesis-Friendly Architecture to Support ASIC Design Methodologies * Up to 100% Resource Utilization and 100% Pin Fixing * Deterministic, User-Controllable Timing * Unique In-System Diagnostic and Verification Capability with Silicon Explorer II * Low Power Consumption * IEEE Standard 1149.1 (JTAG) Boundary Scan Testing * 5.0V and 3.3V Programmable PCI-Compliant I/O
High P er f or m ance
HiR el Feat ur es
* Commercial, Industrial, and Military Temperature Plastic Packages
Pr od uc t P r o f i l e
Capacity
System Gates SRAM Bits
Logic Modules
3,000 N/A -- 295 -- 9.5 ns N/A -- 147 1 57 No No
6,000 N/A -- 547 -- 9.5 ns N/A -- 273 1 69 No No 44, 68, 84 100 80 -- -- --
14,000 N/A 348 336 N/A 5.6 ns N/A 348 516 2 104 No No 84 100, 160 100 176 -- --
24,000 N/A 624 608 N/A 6.1 ns N/A 624 928 2 140 No No 84 100, 160, 208 100 176 -- --
36,000 N/A 954 912 24 6.1 ns N/A 954 1,410 2 176 Yes Yes 84 160, 208 -- 176 -- --
54,000 2,560 1,230 1,184 24 6.3 ns 10 1,230 1,822 6 202 Yes Yes -- 208, 240 -- -- 208, 256 272
Sequential Combinatorial Decode
Clock-to-Out SRAM Modules (64x4 or 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks User I/O (Maximum) PCI
Boundary Scan Test (BST) Packages (by pin count)
w
w
w
.
at d
PLCC PQFP VQFP TQFP CQFP PBGA
sh a
et e
u. 4
om c
44, 68 100 80 -- -- --
F eb r u a r y 2 0 0 1
1
(c) 2001 Actel Corporation
www..com
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
40MX and 42MX FPGA Families
G en er al D e sc r i p t i on
Actel's 40MX and 42MX families provide a high-performance, single-chip solution for shortening the system design and development cycle, offering a cost-effective alternative to ASICs. The 40MX and 42MX devices are excellent choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and co-processor functions. The MX device architecture is based on Actel's patented antifuse technology implemented in a 0.45 triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the synthesis-friendly MX devices provide performance up to 250 MHz, are live on power-up, and require up to five times lower stand-by power consumption than any other FPGA device. Actel's MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades. Actel's 42MX devices also feature MultiPlex I/Os, which support mixed voltage systems, enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a low-power mode. The MX PCI-Compliant devices are fully compliant with the PCI Local Bus Specification (version 2.1). They deliver 200
O r d e r i n g I nf o r m a t i o n
A42MX16 - PQ 100
MHz on-chip operation and 6.1 ns clock-to-output performance with capacities spanning from 36,000 to 54,000 system gates. MX devices comply 100 percent to the electrical and timing specifications detailed in the PCI specification. However, as with all programmable logic devices, the performance of the final product depends upon the user's design and optimization techniques. The MX24 and MX36 devices also include system-level features such as IEEE Standard 1149.1 (JTAG) Boudary Scan Testing, dual-port SRAM, and fast wide-decode modules. The A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide datapath manipulation and can perform transformation functions such as those required for telecommunications, networking, and DSP. All products in the 40MX and 42MX families are available 100 percent tested over the military temperature range. In addition, the largest member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and PQ208 devices are pin compatible.
Application (Temperature Range) Blank = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 Package Lead Count Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack BG = Ball Grid Array CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard -2 = Approximately 25% Faster than Standard -3 = Approximately 35% Faster than Standard -F = Approximately 40% Slower than Standard Part Number A40MX02= A40MX04= A42MX09= A42MX16= A42MX24= A42MX36= 3,000 System Gates 6,000 System Gates 14,000 System Gates 24,000 System Gates 36,000 System Gates 54,000 System Gates
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Pr od uc t P l a n
Speed Grade* Std A40MX02 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) A40MX04 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) 68-Pin Plastic Leaded Chip Carrier (PLCC) 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX09 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX16 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) A42MX24 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 160-Pin Plastic Quad Flat Pack (PQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 176-Pin Thin Plastic Quad Flat Pack (TQFP) A42MX36 Device 208-Pin Plastic Quad Flat Pack (PQFP) 240-Pin Plastic Quad Flat Pack (PQFP) 272-Pin Plastic Ball Grid Array (PBGA) 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) -- -- -- --
-1 -2 -3 -F = = = =
Application -F C I M B
-1
-2
-3

-- --

*
-- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- -- --
-- -- -- --
-- -- -- * *
*
Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available *Speed Grade: I = Industrial P = Planned M = Military -- = Not Planned
Approx. 15% faster than Standard Approx. 25% faster than Standard Approx. 35% faster than Standard Approx. 40% slower than Standard
Only Std, -1, -2 Speed Grade * Only Std, -1 Speed Grade
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40MX and 42MX FPGA Families
D ev el o pm e n t T oo l S up po r t
The MX devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer Series tools. The Actel DeskTOP series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place-and-route tools. Designer Series, Actel's suite of FPGA development point tools for PCs and Workstations, includes the ACTgen Macro Builder, timing-driven place-and-route and analysis tools, and device programming software. In addition, the MX devices contain ActionProbe circuitry that provides built-in access to every node in a design,
Pl a s t i c D e vi c e Re so u r ce s
enabling 100 percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds.
User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44-Pin 34 34 -- -- -- -- PLCC 68-Pin 57 57 -- -- -- -- PLCC 84-Pin -- 69 72 72 72 -- PQFP PQFP PQFP PQFP 100-Pin 160-Pin 208-Pin 240-Pin 57 69 83 83 -- -- -- -- 101 125 125 -- -- -- -- 140 176 176 -- -- -- -- -- 202 VQFP 80-Pin 57 69 -- -- -- -- VQFP TQFP PBGA 100-Pin 176-Pin 272-Pin -- -- 83 83 -- -- -- -- 104 140 150 -- -- -- -- -- -- 202
Package Definitions (Contact your Actel sales representative for product availability.) PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array
C er a m i c De v i ce R es ou r c es
User I/Os Device A42MX36 CQFP CQFP 208-Pin 256-Pin 176 202
Package Definitions (Contact your Actel sales representative for product availability.) CQFP = Ceramic Quad Flat Pack
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Po w e r R eq ui r em e nt s
40MX
M X Ar ch i t e ct u r a l O ve r vi ew
The 40MX FPGAs will operate in 5.0V-only systems or 3.3V-only systems. VCC 5.0V 3.3V
42MX
Input 5.0V 3.3V
Output 5.0V 3.3V
The 42MX FPGAs will operate in 5.0V-only systems, 3.3V-only systems, or mixed 5.0V/3.3V systems. VCCA 5.0V 3.3V 5.0V VCCI 5.0V 3.3V 3.3V Input 5.0V 3.3V 3.3V, 5.0V Output 5.0V 3.3V 3.3V
The 40MX and 42MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within these families are composed of logic modules, I/O modules, routing resources, and clock networks, which are the building blocks for designing fast logic designs. In addition, the A42MX36 device contains embedded dual-port SRAM and wide decode modules. The dual-port SRAM modules are optimized for high-speed datapath functions such as FIFOs, LIFOs, and scratchpad memory. The "Product Profile" on page 1 lists the specific logic resources contained within each device.
Logi c Modu les
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions with different combinations of active LOW inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the array, since latches and flip-flops can be constructed from logic modules wherever needed in the application.
M i xe d Vo l t a ge P ow e r U p an d P o w er D ow n
When powering up the device in the mixed voltage mode (VCCA = 5.0V and VCCI = 3.3V), VCCA must be greater than or equal to VCCI throughout the power-up sequence. If VCCI is 0.5V greater than VCCA when both are above 1.5V, then the I/Os' input protection junction on the I/Os will be forward biased, causing them to draw large amounts of current. When VCCA and VCCI are in the 1.5V to 2.0V region and VCCI is greater than VCCA, all I/Os would momentarily behave as outputs that are in a logical high state, and ICC rises to high levels. For power down, any sequence with VCCA and VCCI can be implemented.
Lo w P ow e r M o de
The 42MX devices have a power-saving feature enabled by a special Low Power pin (LP). In this mode, the device consumes very minimal power, with standby current as low as 15A (see "Electrical Specifications" on page 13 and 14). All I/Os are tristated, all input buffers are turned off, and the core of the device is turned off. Since the core is turned off, the state of the registers and the contents of the SRAM are lost. The device enters low power mode 800ns after the LP pin is set High. It will resume normal operation 200s after the LP pin is driven to a logic Low.
Figure 1 * 40MX Logic Module
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40MX and 42MX FPGA Families
The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules), and decode (D-modules). The C-module, shown in Figure 2, implements the following function: Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11 where S0=A0*B0 S1=A1+B1 The S-module, shown in Figure 3, is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D flip-flop or a transparent latch. To increase flexibility, the S-module register can be bypassed so that it implements purely combinatorial logic.
A0 B0 S0 D00 D01 D10 D11 S1 A1 B1 Y
Figure 2 * C-Module Implementation
D00 D01 D10 D11 S1 Y S0 CLR D Q OUT
D00 D01 D10 D11 S1 Y S0 D GATE Q OUT
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
Up to 7-Input Function Plus Latch
D00 D0 Y D1 S D GATE CLR Q OUT D01 D10 D11 S1 S0 Y OUT
Up to 4-Input Function Plus Latch with Clear
Up to 8-Input Function Same as C-Module)
Figure 3 * S-Module Implementation
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Some of the 42MX devices contain D-modules, which are arranged around the periphery of the devices. D-modules contain wide-decode circuitry, which provides a fast, wide-input AND function similar to that found in product-term architectures (Figure 4). The D-module allows 42MX devices to perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hard-wired to an output pin, but it can also be fed back into the array to be incorporated into other logic.
Dua l- Po rt S R AM Mod ules
offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]) which are connected to segmented vertical routing tracks. The 42MX dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring fast FIFO and LIFO queues. Actel's ACTgen Macro Builder provides the capability to quickly design memory functions, such as FIFOs, LIFOs, and RAM arrays. In addition, unused SRAM blocks can be used to implement registers for other logic within the design.
The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width and depth. A block diagram of the 42MX dual-port SRAM block is shown in Figure 5. The 42MX SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities
7 Inputs
Hard-Wire to I/O Programmable Inverter
Feedback to Array
Figure 4 * D-Module Implementation
WD[7:0]
Latches [7:0]
[5:0] Write Port Logic SRAM Module 32 x 8 or 64 x 4 (256 Bits) Read Port Logic Latches
RDAD[5:0]
WRAD[5:0] Latches
[5:0]
Read Logic
REN RCLK
MODE BLKEN WEN WCLK Write Logic RD[7:0]
Routing Tracks
Figure 5 * 42MX Dual-Port SRAM Block
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40MX and 42MX FPGA Families
Mul ti P lex I/ O M odul es
Horizontal Routing
MultiPlex I/O supports the most common voltage standards today: pure 5.0V operation, pure 3.3V operation, and mixed 3.3V operation with 5.0V I/O tolerance for maximum performance. Internal array performance is retained in 3.3V systems by using complimentary pass gates that operate as fast as they do at 5.0V at 3.3V. MultiPlex I/O includes selectable PCI output drives in certain 42MX devices, enabling 100% PCI-compliance for both 5.0V and 3.3V systems. For low-power systems, MultiPlex I/O is used to turn off all inputs and outputs to cut current consumption to below 100A. The MultiPlex I/O modules provide the interface between the device pins and the logic array. The top of Figure 6 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module. (Refer to the Macro Library Guide for more information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be configured for input, output, or bi-directional operation. All 42MX devices contain flexible I/O structures (Figure 7 on page 9), where each output pin has a dedicated output-enable control. The I/O module can be used to latch input or output data, or both, providing a fast set-up time. In addition, the Actel Designer Series software tools can build a D-type flip-flop using a C-module to register input and output signals. To achieve 5.0V or 3.3V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide PCI fuse is programmed. When the PCI fuse is not programmed, the output drive is standard. (See the bottom portion of Figure 6.) Actel's Designer Series development tools provide a design library of I/O macrofunctions that can implement all I/O configurations supported by the MX FPGAs.
Rou ti ng St r uct ur e
Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third at the row length is considered a long horizontal segment. A typical channel is shown in Figure 8 on page 9. Non-dedicated horizontal routing tracks are used to route signal nets; dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks.
EN
Q From Array
D PAD
G/CLK*
Q To Array
D
G/CLK* * Can be Configured as a Latch or D Flip-Flop (Using C-Module) Schematic STD
Signal Output PCI Drive PCI Enable Fuse
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may be either of continuous length or broken into pieces called segments. Varying segment lengths allows the interconnect of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses.
Figure 6 * 42MX I/O Module
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks: input, output, and long, which are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during
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OE From Internal Logic
internally-generated clock signal to a clock network. Since both clock networks are identical, it does not matter whether CLK0 or CLK1 is being used. The clock input pads can also be used as normal I/Os, bypassing the clock networks (Figure 9). The A42MX36 device has four additional register control resources, called quadrant clock networks (Figure 10 on page 10). Each quadrant clock provides a local, high-fanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable.
Segmented Horizontal Routing Tracks Logic Modules
To Internal Logic
Figure 7 * 40MX I/O Module routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 8.
Antifuse Structures
An antifuse is a "normally open" structure as opposed to the normally connected fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as efficient programming algorithms. The structure is highly-testable because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Cl ock Net wor ks
Antifuses
Vertical Routing Tracks
Figure 8 * Routing Structure
CLKB CLKA From Pads CLKMOD CLKINB CLKINA S0 S1 Internal Signal CLKO(17) Clock Drivers CLKO(16) CLKO(15)
The 40MX devices have one global clock distribution network (CLK). Two low-skew, high-fanout clock distribution networks are provided in each 42MX device. These networks are referred to as CLK0 and CLK1. Each network has a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows: * Externally from the CLKA pad * Externally from the CLKB pad * Internally from the CLKINTA input * Internally from the CLKINTB input The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The user controls the clock module by selecting one of two clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an
CLKO(2) CLKO(1)
Clock Tracks
Figure 9 * Clock Networks
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40MX and 42MX FPGA Families
T est C ir cu it ry
All devices contain Actel's ActionProbe test circuitry which test and debug a design once it is programmed into a device. Once a device has been programmed, the ActionProbe test circuitry allows the designer to probe any internal node during device operation to aid in debugging a design. In addition, 42MX devices contain IEEE Standard 1149.1 boundary scan test circuitry.
IEEE Standard 1149.1 Boundary Scan Testing (BST)
interconnections. The TMS and TCK signals are shared among all devices in the test chain so that all components operate in the same state. The 42MX family implements a subset of the IEEE Standard 1149.1 BST instruction in addition to a private instruction, which allows the use of Actel's ActionProbe facility with BST. Refer to the IEEE Standard 1149.1 specification for detailed information regarding BST.
Boundary Scan Circuitry
IEEE Standard 1149.1 defines a four-pin Test Access Port (TAP) interface for testing integrated circuits in a system. The 42MX family provides five BST pins: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), and Test Mode Select Test Reset (TRST) (42MX24A only). Devices are configured in a test "chain" where BST data can be transmitted serially between devices via TDO-to-TDI
The 42MX boundary scan circuitry consists of a Test Access Port (TAP) controller, test instruction register, a JPROBE register, a bypass register, and a boundary scan register. Figure 11 on page 11 shows a block diagram of the 42MX boundary scan circuitry.
QCLKA Quad Clock Module Quad Clock Module
QCLKC
QCLKB *QCLK1IN
QCLK1
QCLK3
QCLKD *QCLK3IN
S0 S1
S1 S0
Quad Clock Module *QCLK2IN S0 S1
QCLK2
QCLK4
Quad Clock Module *QCLK4IN S1 S0
*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 10 * Quadrant Clock Network
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JPROBE Register Boundary Scan Register Bypass Register Control Logic JTAG TMS
TCK
Output MUX
TDO
TAP Controller
Instruction Decode
JTAG TDI Instruction Register
Figure 11 * 42MX IEEE 1149.1 Boundary Scan Circuitry When a device is operating in BST mode, four I/O pins are used for the TDI, TDO, TMS, and TCK signals. An active reset (nTRST) pin is not supported; however, the 42MX device contain power-on circuitry that resets the boundary scan circuitry upon power-up. Table 1 summarizes the functions of the IEEE 1149.1 BST signals. Table 1 * IEEE 1149.1 BST Signals
Signal TDI Name Test Data In Function Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. Serial data output for BST instructions and test data. Serial data input for BST mode. Data is shifted in on the rising edge of TCK. Clock signal to shift the BST data into the device.
JTAG fuse programmed: * TCK must be terminated--logical high or low doesn't matter (to avoid floating input) * TDI, TMS may float or at logical high (internal pull-up is present) * TDO may float or connect to TDI of another device (it's an output) JTAG fuse not programmed: * TCK, TDI, TDO, TMS are user I/O. If not used, they will be configured as tristated output.
BST Instructions
TDO TMS
Test Data Out Test Mode Select Test Clock
TCK
Boundary scan testing within the 42MX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the testing of the device. The BST mode is determined by the bitstream entered on the TMS pin. Table 2 describes the test instructions supported by the 42MX devices.
Reset
JTAG
All SX-A devices are IEEE 1149.1 (JTAG) compliant. SX-A devices offer superior diagnostic and testing capabilities by providing JTAG and probing capabilites. These functions are controlled through the special JTAG pins in conjunction with the program fuse.
The TMS pin is equipped with an internal pull-up resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five TCK cycles.
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40MX and 42MX FPGA Families
Table 2 * BST Instructions
Test Mode EXTEST Code 000 Description Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Allows a snapshot of the signals at the device pins to be captured and examined during device operation. A private instruction allowing the user to connect Actel's Micro Probe registers to the test chain. Allows the user to build application-specific instructions such as RAM READ and RAM WRITE. Refer to the IEEE Standard 1149.1 specification. Refer to the IEEE Standard 1149.1 specification. Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the test chain.
SAMPLE/ PRELOAD
001
JPROBE
011
USER 100 INSTRUCTION
HIGH Z CLAMP BYPASS
101 110 111
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5 . 0V O p er a t i n g C o nd i t i o ns a nd M i xe d 5. 0 V / 3. 3 V Op e r at i ng C on di t i on s A bs o l ut e M a xi m u m R at i ng s 1
Free Ai r Tem per at ure Rang e
R e co m m e nd e d O p era t i n g C o nd i t i o ns
Parameter Commercial Industrial 0 to +70 5 4.75 to 5.25 4.75 to 5.25 3.14 to 3.47 Military Units C %VCC V V V
Symbol Parameter VCCA/ VCCI VI VO TSTG DC Supply Voltage Input Voltage Output Voltage Storage Temperature
Limits -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150
Units V V V C
Temperature Range1 Power Supply Tolerance VCCI VCCA VCCI2
-40 to +85 -55 to +125 10 4.5 to 5.5 4.5 to 5.5 3.0 to 3.6 10 4.5 to 5.5 4.5 to 5.5 3.0 to 3.6
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCCA + 0.5V or less than GND - 0.5V, the internal protection diode will be forward-biased and can draw excessive current.
Notes: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. 2. Operating condition for I/Os in mixed voltage mode.
E l ec t r i c a l Sp e ci f i c a t i on s
Commercial Symbol VOH1 Parameter Min. (IOH = -10 mA) 2 TTL (IOH = -6 mA) TTL (IOH = -4 mA) TTL VOL VIL VIH IIL IIH CIO I/O (VIN = 0.5) (VIN = 2.7)
2 1
Commercial `-F' Min. 2.4 Max.
Industrial Min. Max.
Military Units Min. Max. V V
Max.
2.4
3.7 0.5 0.5 0.40 -0.3 2.0 0.8 VCCI + 0.3 -10 -10 500 10 Notes 5 & 6 -0.3 2.0 0.8 VCCI + 0.3 -10 -10 500 10 25.0 -0.3 2.0 0.8 VCCI + 0.3 -10 -10 500 10 Notes 6 & 7
3.7
V V 0.40 V V V A A ns pF mA
(IOL = 10
mA) 2 TTL
(IOL = 6 mA) TTL
-0.3 2.0
0.8 VCCI + 0.3 -10 -10 500 10 25
Input Transition Time tR, tF Capacitance2, 3
4
Standby Current, ICC
ICC(D) Dynamic VCCI Supply Current Low Power Mode Standby Current Note 8
See the "Power Dissipation" section on page 18. ICC - 0.5 ICC - 0.5 ICC - 0.5 mA
Notes: 1. Only one output tested at a time. VCCI = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. All outputs unloaded. All inputs = VCCI or GND. ICC limit includes IPP and ISV during normal operation. 5. A40MX02 and A40MX04 ICC = 3 mA, A42MX09 ICC = 5 mA, A42MX16 ICC = 6 mA, A42MX24, A42MX24A, and A42MX36 ICC = 25 mA. 6. ICC Max = 2 mA is available by special request. Contact your local Actel Sales representative for additional information. 7. A40MX02 and A40MX04 ICC = 10 mA, A42MX09, A42MX16, A42MX24, A42MX24A, and A42MX36 ICC = 25 mA. 8. In Low Power Mode, A42MX09 ICC = 50 A; A42MX16, A42MX24, and A42MX36 ICC = 100 A. A40MX02 and A40MX04 = N/A.
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3. 3 V O pe r a t i ng C on d i t i on s A bs ol u t e M ax i m u m Ra t i n gs 1
V C C = V C C A and V C C I Fr ee Air Te m per at ure R ange
R ec o m m en d ed O pe r a t i ng C on d i t i o ns
Parameter Temperature Range1 Power Supply Tolerance VCCI VCCA Commercial Industrial 0 to +70 5 3.0 to 3.6 3.0 to 3.6 -40 to +85 10 3.0 to 3.6 3.0 to 3.6 Military -55 to +125 10 3.0 to 3.6 3.0 to 3.6 Units C %V V V
Symbol VCC VI VO IIO TSTG
Parameter DC Supply Voltage Input Voltage Output Voltage I/O Source Sink Current2 Storage Temperature
Limits -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 -65 to +150
Units V V V mA C
Note: 1. Ambient temperature (TA) is used for commercial, and industrial; case temperature (TC) is used for military.
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5V or less than GND - 0.5V, the internal protection diodes will forward-bias and can draw excessive current.
El e c t r i c al S p ec i f i c at i o n s
Commercial Parameter Min. VOH1 VOL1 VIL VIH IIL IIH Input Transition Time tR, tF CIO I/O Capacitance2, 3
4 2
Commercial `-F' Min. 2.15 2.4 Max.
Industrial Min. 2.4 Max.
Military Units Min. 2.4 Max. V V
Max.
(IOH = -4 mA) (IOH = -3.2 mA) (IOL = 6 mA)
2.15 2.4 0.4 -0.3 2.0 0.8 VCC + 0.3 -10 -10 500 10 Notes 5 & 6
0.4 -0.3 2.0 0.8 VCC + 0.3 -10 -10 500 10 25 -0.3 2.0
0.48 0.8 VCC + 0.3 -10 -10 500 10 Notes 6 & 7 -0.3 2.0
0.48 0.8 VCC + 0.3 -10 -10 500 10 25
V V V A A ns pF mA
Standby Current, ICC
ICC(D) Dynamic VCC Supply Current Low Power Mode Standby Current Note 8
See the "Power Dissipation" section on page 18. ICC - 5.0 ICC - 5.0 ICC - 5.0 mA
Notes: 1. Only one output IV curve tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. All outputs unloaded. All inputs = VCC or GND. 5. A40MX02 and A40MX04 ICC = 3 mA, A42MX09 ICC = 5 mA, A42MX16 ICC = 6 mA, A42MX24 and A42MX36 ICC = 25 mA. 6. ICC Max = 1.5mA is available by special request. Contact your Actel Sales representative for additional information. 7. A40MX02 and A40MX04 ICC = 10 mA, A42MX09, A42MX16, A42MX24, and A42MX36 ICC = 25 mA. 8. In Low Power Mode, A42MX09 ICC = 15 A; A42MX16, A42MX24, A42MX36 ICC = 50 A. A40MX02 and A40MX04 = N/A.
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O ut p u t D r i ve C ha r a ct e r i s t i c s f o r 5. 0 V PC I S i g na l i n g
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 12 on page 17 shows the typical output drive characteristics of the MX devices. MX output drivers are compliant with the PCI Local Bus Specification.
DC S pec if i cat ion (5. 0V P CI S igna li ng) 1
PCI Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK LPIN Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Pin Inductance 5 VIN = 2.7 VIN=0.5 IOUT = -2 mA IOUT = -6 mA IOUT = 3 mA, 6 mA 0.55 10 12 20 2.4 3.84 -- -- -- -- Condition Minimum 4.75 2.0 -0.5 Maximum 5.25 VCC + 0.5 0.8 70 -70 Minimum 4.75 2.0 -0.3 -- --
MX Maximum 5.25
2
Units V V V A A V
VCC + 0.3 0.8 10 -10
0.33 10 10 <8 nH3
V pF pF nH
Notes: 1. PCI Local Bus Specification Section 4.2.1.1. 2. Maximum rating for VCC -0.5V to 7.0V. 3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
AC S pec if i cat ion s (5.0 V P C I S i gnal ing ) 1
PCI Symbol ICL Slew (r) Slew (f) Parameter Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition -5 < VIN -1 0.4V to 2.4V load 2.4V to 0.4V load Minimum -25 + (VIN +1) /0.015 1 1 5 5 Maximum
MX Minimum -60 1.8 2.8 Maximum -10 2.8 4.3 Units mA V/ns V/ns
Note: 1. PCI Local Bus Specification Section 4.2.1.2.
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O ut p u t D r i ve C ha r a ct e r i s t i c s f o r 3 . 3V P C I Si gn al i n g
DC S pec if i cat ion (3. 3V P CI S igna li ng) 1
PCI Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK LPIN Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Pin Inductance 5 IOUT = -2 mA IOUT = 3 mA, 6 mA 0.9 0.1 10 12 20 VIN = 2.7 Condition Minimum 3.0 0.5 -0.5 Maximum 3.6 VCC + 0.5 0.8 70 -70 3.3 Minimum 3.0 0.5 -0.3
MX Maximum 3.6 VCC + 0.3 0.8 10 -10 Units V V V A A V 0.1 VCC 10 10 <8 nH3 V pF pF nH
Notes: 1. PCI Local Bus Specification Section 4.2.2.1. 2. Maximum rating for VCC -0.5V to 7.0V. 3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
AC S pec if i cat ion s for (3. 3V P CI S igna li ng) 1
PCI Symbol ICL Slew (r) Slew (f) Parameter Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition -5 < VIN -1 0.2V to 0.6V load 0.6V to 0.2V load Minimum -25 + (VIN +1) /0.015 1 1 4 4 Maximum
MX Minimum -60 1.8 2.8 Maximum -10 2.8 4.0 Units mA V/ns V/ns
Note: 1. PCI Local Bus Specification Section 4.2.2.2.
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0.50 0.45 0.40 0.35 0.30 0.25 0.20 Current (A) 0.15 0.10
PCI IOL Maximum
MX PCI IOL
PCI IOL Minimum
0.05 0.00
0 1 2 3 4 5 6
-0.05 -0.10 -0.15 -0.20
PCI IOH Maximum
MX PCI IOH
PCI IOH Minimum
Voltage Out (V)
Figure 12 * Typical Output Drive Characteristics (Based upon measured data)
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Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.
Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows:
Max. junction temp. (C) - Max. commercial temp. ---------------------------------------------------------------------------------------------------------------------------- = 150C - 70C = 2.5W -------------------------------- ja (C/W) 32C/W Plastic Packages Pin Count Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Plastic Ball Grid Array Ceramic Packages Ceramic Quad Flat Pack Ceramic Quad Flat Pack Pin Count 208 256 100 160 208 240 44 68 84 176 80 100 272
ja jc
12 10 8 3.5 16 13 12 11 12 10 3 Still Air 34C/W 32C/W 30C/W 19C/W 43C/W 36C/W 32C/W 28C/W 39C/W 38C/W 20C/W 300 ft/min 31C/W 24C/W 23C/W 16C/W 31C/W 25C/W 22C/W 21C/W 33C/W 32C/W 14.5C/W
jc
6.3 6.2
ja
Still Air 22C/W 20C/W
S t at ic Po wer C om pon ent
Po w e r D i ss i pa t i o n
Gener al P ow er E quat i on
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N + IOH * (VCCI - VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on design details, and on the system I/O. The power can be divided into two components: static and active.
Actel FPGAs have small static power components that result in power dissipation lower than PALs or CPLDs. By integrating multiple PALs/CPLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated for commercial, worst-case conditions: ICC 2 mA VCCA 5.25 V Power 10.5 mW
The static power dissipation by TTL loads depends on the number of outputs driving HIGH or LOW, and on the DC load current. Again, this number is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving LOW, and 140 mW with all outputs driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.
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Act i ve P ower C om po nent
where: = Number of logic modules switching at frequency fm = Number of input buffers switching at frequency fn = Number of output buffers switching at frequency fp = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock r1 = Fixed capacitance due to first routed array clock r2 = Fixed capacitance due to second routed array clock CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL = Output load capacitance in p fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz
Fix ed Capa cit anc e V alu es for M X F PG As (pF )
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent and a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation.
E quiv al ent C apac it ance
m n p q1
The power dissipated by a CMOS circuit can be expressed by the equation: Power (W) = CEQ * VCCA2 * F where: CEQ = Equivalent capacitance expressed in picofarads (pF) = Switching frequency in megahertz (MHz) (1)
VCCA = Power supply in volts (V) F Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below.
C E Q Valu es f or A ct el MX FP G A s
Device Type A40MX02 A40MX04
r1 routed_Clk1 41.4 68.6 118 165 185 220
r2 routed_Clk2 N/A N/A 118 165 185 220
Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR)
3.5 6.9 18.2 1.4
A42MX09 A42MX16 A42MX24 A42MX36
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. The equation below shows a piece-wise linear summation over all components. Power = VCCA2 * [(m x CEQM * fm)Modules + (n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
(2)
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40MX and 42MX FPGA Families
Det er m ini ng Av er age S wi tch ing Frequ ency
To determine the switching frequency for a design, the data input values to the circuit must be clearly understood. The following guidelines represent worst-case scenarios; these can be used to generally predict the upper limits of power dissipation. Logic Modules (m) = 80% of Combinatorial Modules = # of Inputs/4 = # of Outputs/4 = 40% of Sequential Modules = 40% of Sequential Modules = 35 pF
Logic Modules (m)
= 80% of Combinatorial Modules = F/10 = F/5 = F/10 =F = F/2
Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2)
Inputs Switching (n) Outputs Switching (p) First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL)
40 M X Ti m i ng M od e l *
Input Delay I/O Module tINYL = 0.62 ns t IRD2 = 2.59 ns
Internal Delays
Predicted Routing Delays
Output Delay I/O Module
Logic Module tDLH = 3.32 ns tIRD1 = 2.09 ns tIRD4 = 3.64 ns tIRD8 = 5.73 ns tPD = 1.24 ns tCO = 1.24 ns tRD1 = 1.28 ns tRD2 = 1.80 ns tRD4 = 2.33 ns tRD8 = 4.93 ns tENHZ = 7.92 ns
Array Clock
tCKH = 4.55 ns FMAX = 180 MHz
FO = 128
* Values are shown for 40MX `-3' speed devices at 5.0V worst-case commercial conditions.
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42 M X Ti m i ng M od e l *
Input Delays I/O Module tINYL = 1.16 ns tIRD1 = 2.24 ns Combinatorial Logic Module D Q tPD = 1.55 ns tRD1 = 0.80 ns tRD2 = 1.00 ns tRD4 = 1.50 ns tRD8 = 2.50 ns Internal Delays Predicted Routing Delays Output Delays I/O Module
tDLH = 2.70 ns
G tINH = 0.00 ns tINSU = 0.54 ns tINGL = 1.40 ns Sequential Logic Module
Combinatorial Logic included in tSUD
I/O Module tDLH = 2.70 ns
D
Q tRD1 = 0.80 ns
D
Q tENHZ = 5.40 ns
G tOUTH = 0.00 ns tOUTSU = 0.30 ns tGLH = 2.90 ns
Array Clocks
tCKH = 2.70 ns FMAX = 245 MHz
FO = 32
tSUD = 0.36 ns tHD = 0.00 ns
tCO = 1.37 ns
tLCO = 5.60 ns (light loads, pad-to-pad)
*Values are shown for A42MX09 `-2' at 5.0V worst-case commercial conditions Input module predicted routing delay
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42 M X Ti m i ng M od e l ( Lo g i c F un c t i on s us i ng Q ua dr an t C l o ck s) *
Input Delays I/O Module tINPY = 1.14 ns t IRD1 = 2.18 ns Combinatorial Module D Q tPD = 1.46 ns tRD1 = 1.04 ns tRD2 = 1.42 ns tRD4 = 2.18 ns Internal Delays Predicted Routing Delays Output Delays I/O Module
tDLH = 2.84 ns
G tINH = 0.00 ns tINSU = 0.53 ns tINGO = 1.55 ns Decode Module tPDD = 1.78 ns I/O Module tDLH = 2.84 ns
tRDD = 0.38 ns
Sequential Logic Module
Combinatorial Logic included in tSUD
D
Q
tRD1 = 1.04 ns
D
Q tENHZ = 5.80 ns
G tLH = 0.00 ns tLSU = 0.53 ns tGHL= 3.27 ns
tSUD = 0.30 ns tHD = 0.00 ns Quadrant Clocks tCKH = 3.03 ns** FMAX = 163 MHz
tCO = 1.43 ns
* Preliminary values are shown for A42MX36 `-2' at 5.0V worst-case commercial conditions ** Load-dependent
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42 M X Ti m i ng M od e l ( SR A M F un ct i on s) *
Input Delays I/O Module tINPY = 1.14 ns t IRD1 = 2.18 ns
D
Q
G tINSU = 0.53 ns tINH = 0.00 ns tINGO = 1.55 ns
Predicted Routing Delays WD [7:0] WRAD [5:0] BLKEN WEN WCLK tADSU = 1.80 ns tADH = 0.00 ns tWENSU = 2.90 ns tBENS = 2.90 ns RD [7:0] RDAD [5:0] REN tRD1 = 1.04 ns
I/O Module tDLH = 2.84 ns
D
Q
RCLK tADSU = 1.80 ns tADH = 0.00 ns tRENSU = 0.80 ns tRCO = 3.80 ns
G tGHL= 5.50 ns tLSU = 0.30 ns tLH = 0.00 ns
Array Clocks FMAX = 151 MHz
*Values are shown for A42MX36 `-2' at 5.0V worst-case commercial conditions.
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P ar am e t e r M ea s ur e m e nt
O ut put Buf f er De lay s
E D TRIBUFF PAD To AC test loads (shown below)
In PAD VOL
50%
50% VOH 1.5V 1.5V
E PAD
50% VCCI
50% 1.5V VOL 10% tENLZ
E PAD GND
50%
50% VOH 1.5V 90% tENHZ
tDLH
tDHL
tENZL
tENZH
A C Tes t Loa ds
Load 1 (Used to measure propagation delay)
Load 2 (Used to measure rising/falling edges) VCCI GND
To the output under test
35 pF To the output under test
R to VCCI for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k 35 pF
Inp ut Bu ff er D ela ys
Modu le Del ay s
PAD
INBUF
Y
S A B
Y
S, A or B 3V PAD Y GND tINYH 1.5V 1.5V VCCI 50% tINYL 0V 50% Y
50% 50% 50% tPLH tPHL 50% tPLH 50%
Y 50% tPHL
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S eq u en t i a l M od ul e T i m i ng C ha r a ct er i st i c s
Fl ip- Fl ops and La tch es
D E CLK
PRE CLR
Y
(Positive Edge-Triggered)
tHD D
1
tSUD G, CLK
tWCLKA tSUENA tHENA
tA
tWCLKI
E tCO Q tRS PRE, CLR tWASYN Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
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40MX and 42MX FPGA Families
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Inpu t Buffer Lat ch es
DATA
PAD G
IBDL
CLK
PAD CLKBUF
DATA tINH G tINSU tHEXT CLK tSUEXT
Out put B uffer L at ches
D OBDLHS G
PAD
D tOUTSU G tOUTH
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D ec od e M od ul e T i m i ng
A B C D E F G
Y H
A-G, H
50%
Y tPHL tPLH
SR A M T i m i ng C ha r a ct er i s t i c s
Write Port WRAD [5:0] BLKEN WEN WCLK WD [7:0] RAM Array 32x8 or 64x4 (256 Bits)
Read Port RDAD [5:0] LEW REN RCLK RD [7:0]
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D ua l - Po r t S R A M Ti m i n g W av ef or m s
42MX S R AM Wr it e O per at ion
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU WEN tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing for falling edge clock.
42MX S R AM S ync hronou s Rea d Ope ra ti on
tCKHL RCLK
tRCKHL
tRENSU REN tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Old Data New Data
Note:
Identical timing for falling edge clock.
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42MX S R AM As yn chrono us Re ad Op er ati on-- Typ e 1
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data 1 ADDR2 tRPD Data 2
42MX S R AM As yn chrono us Re ad Op er ati on-- Typ e 2
(Write Address Controlled)
WEN
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Old Data
New Data
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Pr ed i ct ab l e Pe rf o r m a nc e: Ti g h t D el a y D i s t r i b ut i on s
Lo ng T r ack s
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented antifuse offers a very low resistive/capacitive interconnect. The antifuses, fabricated in 0.45 lithography, offer nominal levels of 100 3/4 resistance and 7.0 femtofarad (fF) capacitance per antifuse. MX fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90 percent of interconnects using only two antifuses.
Ti m i ng C ha r a ct e r i s t i c s
Some nets in the design use long tracks, which are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section, beginning on page 34.
T im i ng Der at in g
A timing derating factor of 0.45 is used to reflect best-case processing. Note that this factor is relative to the standard speed timing parameters and must be multiplied by the appropriate voltage and temperature derating factors for a given application.
T i m i n g D e r at i ng Fa c t or s
C om m er cial t o Indus t ri al
Industrial Min. (Commercial Specification) x 0.69 Max. 1.11
C om m er cial W o rs t- Ca se t o T y pica l
Device timing characteristics fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all MX devices. For mixed voltage of the A42MX devices, the timing numbers are defined in the 3.3V section for I/Os while for the internal logic resources, the timing numbers are defined in the 5.0V section. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after place-and-route of the user's design is complete. Delay values may then be determined by using the Designer Series utility or by performing simulation with post-layout delays.
Cr it ic al Net s and Ty pi cal Net s
Commerical Typical (TJ = 25C, VCC = 5.0V) (Commercial, Worst-Case Condition) x Note: 0.85
This derating factor applies to all routing and propagation delays.
Propagation delays in this data sheet apply to typical nets. The abundant routing resources in the MX architecture allows for deterministic timing using Actel's Designer Series development tools, which include TDPR, a timing-driven place-and-route tool. Using Timer, the designer can specify timing-critical nets and system clock frequency. Using these timing specifications, the place-and-route software optimizes the layout of the design to meet the user's specifications.
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42 M X Te m p era t u r e an d Vo l t a ge D era ti n g Fa ct ors
(Normalized to T J = 25C, V CCA /V C CI = 5.0V)
42MX Voltage 4.50 4.75 5.00 5.25 5.50
Temperature -55C 0.93 0.88 0.85 0.84 0.83 -40C 0.95 0.90 0.87 0.86 0.85 0C 1.05 1.00 0.96 0.95 0.94 25C 1.09 1.03 1.00 0.97 0.96 70C 1.25 1.18 1.15 1.12 1.10 85C 1.29 1.22 1.18 1.14 1.13 125C 1.41 1.34 1.29 1.28 1.26
(Normalized to TJ = 25C, VCCA/VCCI = 5.0V)
1.50 1.40
Derating Factor
1.30 -55 C 1.20 -40 C 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50 0C 25 C 70 C 85 C 125 C
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
v5.0
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40MX and 42MX FPGA Families
40 M X Te m p era t u r e an d V o l t a ge D era ti n g Fa ct ors
(Normalized to T J = 25C, V CCA /V C CI = 5.0V)
40MX Voltage 4.50 4.75 5.00 5.25 5.50
Temperature -55C 0.89 0.84 0.82 0.80 0.79 -40C 0.93 0.88 0.85 0.82 0.82 0C 1.02 0.97 0.94 0.91 0.90 25C 1.09 1.03 1.00 0.97 0.96 70C 1.25 1.18 1.15 1.12 1.10 85C 1.31 1.24 1.20 1.16 1.15 125C 1.45 1.37 1.33 1.29 1.28
40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25C, VCCA/VCCI = 5.0V)
1.50 1.40
Derating Factor
1.30 -55 C 1.20 -40 C 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50 0C 25 C 70 C 85 C 125 C
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
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PC I S ys t e m T i m i ng S pe ci f i ca t i o n
PC I M o d el s
Table 3 and Table 4 list the critical PCI timing parameters and the corresponding timing parameter for the MX PCI-compliant devices. Table 3 * Clock Specification for 33 MHz PCI
Actel provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI Target and Target+DMA Master interface. Contact your Actel sales representative for more details.
PCI Symbol TCYC THIGH TLOW Parameter CLK Cycle Time CLK High Time CLK Low Time Min. 30 11 11 Max. -- -- --
A42MX24 Min. 4.0 1.9 1.9 Max. -- -- --
A42MX36 Min. 4.0 1.9 1.9 Max. -- -- -- Units ns ns ns
Table 4 * Timing Parameters for 33 MHz PCI
PCI Symbol TVAL TVAL(PTP) TON TOFF TSU TSU(PTP) TH Parameter CLK to Signal Valid--Bused Signals CLK to Signal Valid--Point-to-Point Float to Active Active to Float Input Set-Up Time to CLK--Bused Signals Input Set-Up Time to CLK--Point-to-Point Input Hold to CLK Min. 2 2 2 -- 7 10, 12 0 Max. 11 12 -- 28 -- -- -- A42MX24 Min. 2.0 2.0 2.0 -- 1.5 1.5 0 Max. 9.0 9.0 4.0 8.31 -- -- -- A42MX36 Min. 2.0 2.0 2.0 -- 1.5 1.5 0 Max. 9.0 9.0 4.0 8.31 -- -- -- Units ns ns ns ns ns ns ns
Note: 1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
v5.0
33
40MX and 42MX FPGA Families
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.2 2.7 1.2 1.2 1.2
1.4 3.1 1.4 1.4 1.4
1.6 3.5 1.6 1.6 1.6
1.9 4.1 1.9 1.9 1.9
2.7 5.7 2.7 2.7 2.7
ns ns ns ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
1.3 1.8 2.3 2.9 4.9
1.5 2.1 2.7 3.3 5.7
1.7 2.4 3.0 3.7 6.5
2.0 2.8 3.6 4.4 7.6
2.8 3.9 5.0 6.1 10.6
ns ns ns ns ns
Logic Module Sequential tSUD tHD
3
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128)
3.1 0.0 3.1 0.0 3.3 3.3 4.8 181
3.5 0.0 3.5 0.0 3.8 3.8 5.6 168
4.0 0.0 4.0 0.0 4.3 4.3 6.3 154
4.7 0.0 4.7 0.0 5.0 5.0 7.5 134
6.6 0.0 6.6 0.0 7.0 7.0 10.4 80
ns ns ns ns ns ns ns MHz
tSUENA tHENA tWCLKA tWASYN tA fMAX
Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
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v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y LOW Delays1 2.1 2.6 3.1 3.6 5.7 2.4 3.0 3.6 4.2 6.6 2.2 3.4 4.1 4.8 7.5 3.2 4.0 4.8 5.6 8.8 4.5 5.6 6.7 7.8 12.4 ns ns ns ns ns 0.7 0.6 0.8 0.7 0.9 0.8 1.1 1.0 1.5 1.3 ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to HIGH Input High to LOW FO = 16 FO = 128 FO = 16 FO = 128 2.2 2.4 2.2 2.4 0.4 0.5 4.7 4.8 188 181 5.4 5.6 175 168 4.6 4.6 4.8 4.8 2.6 2.7 2.6 2.7 0.5 0.6 6.1 6.3 160 154 5.3 5.3 5.6 5.6 2.9 3.1 2.9 3.01 0.5 0.7 7.2 7.5 139 134 6.0 6.0 6.3 6.3 3.4 3.6 3.4 3.6 0.6 0.8 10.0 10.4 83 80 7.0 7.0 7.4 7.4 4.8 5.1 4.8 5.1 0.8 1.2 9.8 9.8 10.4 10.4 ns ns ns ns ns ns MHz
Minimum Pulse Width HIGH FO = 16 FO = 128 Minimum Pulse Width LOW FO = 16 FO = 128 Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
35
40MX and 42MX FPGA Families
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW Timing1 3.9 3.4 3.4 4.9 7.9 5.9 0.03 0.02 4.5 3.9 3.9 5.6 9.1 6.8 0.04 0.02 5.1 4.4 4.4 6.4 10.4 7.7 0.04 0.03 6.05 5.2 5.2 7.5 12.2 9.0 0.05 0.03 8.5 7.3 7.3 10.5 17.0 12.6 0.07 0.04 ns ns ns ns ns ns ns/pF ns/pF 3.3 4.0 3.7 4.7 7.9 5.9 0.02 0.03 3.8 4.6 4.3 5.4 9.1 6.8 0.02 0.03 4.3 5.2 4.9 6.1 10.4 7.7 0.03 0.03 5.1 6.1 5.8 7.2 12.2 9.0 0.03 0.04 7.2 8.6 8.0 10.1 17.1 12.6 0.04 0.06 ns ns ns ns ns ns ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW
Note: 1. Delays based on 35 pF loading.
36
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.7 3.7 1.7 1.7 1.7
2.0 4.3 2.0 2.0 2.0
2.3 4.9 2.3 2.3 2.3
2.7 5.7 2.7 2.7 2.7
3.7 8.0 3.7 3.7 3.7
ns ns ns ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
2.0 2.7 3.4 4.2 7.1
2.2 3.1 3.9 4.8 8.2
2.5 3.5 4.4 5.4 9.2
3.0 4.1 5.2 6.3 10.9
4.2 5.7 7.3 8.9 15.2
ns ns ns ns ns
Logic Module Sequential tSUD tHD
3
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128)
4.3 0.0 4.3 0.0 4.6 4.6 6.8 109
4.9 0.0 4.9 0.0 5.3 5.3 7.8 101
5.6 0.0 5.6 0.0 6.0 6.0 8.9 92
6.6 0.0 6.6 0.0 7.0 7.0 10.4 80
9.2 0.0 9.2 0.0 9.8 9.8 14.6 48
ns ns ns ns ns ns ns MHz
tSUENA tHENA tWCLKA tWASYN tA fMAX
Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
v5.0
37
40MX and 42MX FPGA Families
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y LOW Delays1 2.9 3.6 4.4 5.1 8.0 3.4 4.2 5.0 5.9 9.26 3.8 4.8 5.7 6.7 10.5 4.5 5.6 6.7 7.8 12.6 6.3 7.8 9.4 11.0 17.3 ns ns ns ns ns 1.0 0.9 1.1 1.0 1.3 1.1 1.5 1.3 2.1 1.9 ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 6.5 6.8 113 109 3.1 3.3 3.1 3.3 0.6 0.8 7.5 7.8 105 101 6.4 6.4 6.7 6.7 3.6 3.8 3.6 3.8 0.6 0.9 8.5 8.9 96 92 7.4 7.4 7.8 7.8 4.1 4.3 4.1 4.3 0.7 1.0 10.1 10.4 83 80 8.3 8.3 8.8 8.8 4.8 5.1 4.8 5.1 0.8 1.2 14.1 14.6 50 48 9.8 9.8 10.4 10.4 6.7 7.1 6.7 7.1 1.2 1.6 13.7 13.7 14.5 14.5 ns ns ns ns ns ns MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
38
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW Timing1 5.5 4.8 4.7 6.8 11.1 8.2 0.05 0.03 6.4 5.5 5.5 7.9 12.8 9.5 0.05 0.03 7.2 6.2 6.2 8.9 14.5 10.7 0.06 0.04 8.5 7.3 7.3 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns ns ns ns ns ns ns/pF ns/pF 4.7 5.6 5.2 6.6 11.1 8.2 0.03 0.04 5.4 6.4 6.0 7.6 12.8 9.5 0.03 0.04 6.1 7.3 6.8 8.6 14.5 10.7 0.04 0.05 7.2 8.6 8.1 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns ns ns ns ns ns ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW
Note: 1. Delays based on 35 pF loading.
v5.0
39
40MX and 42MX FPGA Families
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.2 2.3 1.2 1.2 1.2
1.4 3.1 1.4 1.4 1.4
1.6 3.5 1.6 1.6 1.6
1.9 4.1 1.9 1.9 1.9
2.7 5.7 2.7 2.7 2.7
ns ns ns ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
1.2 1.9 2.4 2.9 5.0
1.6 2.2 2.8 3.4 5.8
1.8 2.5 3.2 3.9 6.6
2.1 2.9 3.7 4.5 7.8
3.0 4.1 5.2 6.3 10.9
ns ns ns ns ns
Logic Module Sequential tSUD tHD
3
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128)
3.1 0.0 3.1 0.0 3.3 3.3 4.8 181
3.5 0.0 3.5 0.0 3.8 3.8 5.6 167
4.0 0.0 4.0 0.0 4.3 4.3 6.3 154
4.7 0.0 4.7 0.0 5.0 5.0 7.5 134
6.6 0.0 6.6 0.0 7.0 7.0 10.4 80
ns ns ns ns ns ns ns MHz
tSUENA tHENA tWCLKA tWASYN tA fMAX
Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
40
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y LOW Delays1 2.1 2.6 3.1 3.6 5.7 2.4 3.0 3.6 4.2 6.6 2.2 3.4 4.1 4.8 7.5 3.2 4.0 4.8 5.6 8.8 4.5 5.6 6.7 7.8 12.4 ns ns ns ns ns 0.7 0.6 0.8 0.7 0.9 0.8 1.1 1.0 1.5 1.3 ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input LOW to HIGH Input HIGH to LOW FO = 16 FO = 128 FO = 16 FO = 128 2.2 2.4 2.2 2.4 0.4 0.5 4.7 4.8 188 181 5.4 5.6 175 168 4.6 4.6 4.8 4.8 2.6 2.7 2.6 2.7 0.5 0.6 6.1 6.3 160 154 5.3 5.3 5.6 5.6 2.9 3.1 2.9 3.1 0.5 0.7 7.2 7.5 139 134 6.0 6.0 6.3 6.3 3.4 3.6 3.4 3.6 0.6 0.8 10.1 10.4 83 80 7.1 7.1 7.5 7.5 4.8 5.1 4.8 5.1 0.8 1.2 9.9 9.9 10.4 10.4 ns ns ns ns ns ns MHz
Minimum Pulse Width HIGH FO = 16 FO = 128 Minimum Pulse Width LOW FO = 16 FO = 128 Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
41
40MX and 42MX FPGA Families
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW Timing1 3.9 3.4 3.4 4.9 7.9 5.0 0.03 0.02 4.5 3.9 3.9 5.6 9.1 6.8 0.04 0.02 5.1 4.4 4.4 6.4 10.4 7.7 0.04 0.03 6.1 5.2 5.2 7.5 12.2 9.0 0.05 0.03 8.5 7.3 7.3 10.5 17.1 12.6 0.07 0.04 ns ns ns ns ns ns ns/pF ns/pF 3.3 4.0 3.7 4.7 7.9 5.9 0.02 0.02 3.8 4.6 4.3 5.4 9.1 6.8 0.02 0.03 4.3 5.2 4.9 6.1 10.4 7.7 0.03 0.03 5.1 6.1 5.8 7.2 12.2 9.0 0.03 0.04 7.2 8.6 8.1 10.1 17.1 12.6 0.04 0.06 ns ns ns ns ns ns ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW
Note: 1. Delays based on 35 pF loading.
42
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.7 3.7 1.7 1.7 1.7
2.0 4.3 2.0 2.0 2.0
2.3 4.9 2.3 2.3 2.3
2.7 5.7 2.7 2.7 2.7
3.7 8.0 3.7 3.7 3.7
ns ns ns ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
1.9 2.7 3.4 4.1 7.1
2.2 3.1 3.9 4.8 8.1
2.5 3.5 4.4 5.4 9.2
3.0 4.1 5.2 6.3 10.9
4.2 5.7 7.3 8.9 15.2
ns ns ns ns ns
Logic Module Sequential tSUD tHD
3
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128)
4.3 0.0 4.3 0.0 4.6 4.6 6.8 109
5.0 0.0 5.0 0.0 5.3 5.3 7.8 101
5.6 0.0 5.6 0.0 5.6 5.6 8.9 92
6.6 0.0 6.6 0.0 7.0 7.0 10.4 80
9.2 0.0 9.2 0.0 9.8 9.8 14.6 48
ns ns ns ns ns ns ns MHz
tSUENA tHENA tWCLKA tWASYN tA fMAX
Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility. 3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
v5.0
43
40MX and 42MX FPGA Families
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y LOW Delays1 2.9 3.6 4.4 5.1 8.0 3.34 4.2 5.0 5.9 9.3 3.8 4.8 5.7 6.7 10.5 4.5 5.6 6.7 7.8 12.4 6.3 7.8 9.4 11.0 17.2 ns ns ns ns ns 1.0 0.9 1.1 1.0 1.3 1.1 1.5 1.3 2.1 1.9 ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 6.5 6.8 113 109 3.1 3.3 3.1 3.3 0.6 0.8 7.5 7.8 105 101 6.4 6.4 6.8 6.8 3.6 3.8 3.6 3.8 0.6 0.9 8.5 8.9 96 92 7.4 7.4 7.8 7.8 4.1 4.3 4.1 4.3 0.7 1.0 10.1 10.4 83 80 8.4 8.4 8.9 8.9 4.8 5.1 4.8 5.1 0.8 1.2 14.1 14.6 50 48 9.9 9.9 10.4 10.4 6.7 7.1 6.7 7.1 1.2 1.6 13.8 13.8 14.6 14.6 ns ns ns ns ns ns MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
44
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW Timing1 5.5 4.8 4.7 6.8 11.1 8.2 0.05 0.03 6.4 5.5 5.5 7.9 12.8 9.5 0.05 0.03 7.2 6.2 6.2 8.9 14.5 10.7 0.06 0.04 8.5 7.3 7.3 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns ns ns ns ns ns ns/pF ns/pF 4.7 5.6 5.2 6.6 11.1 8.2 0.03 0.04 5.4 6.4 6.0 7.6 12.8 9.5 0.03 0.04 6.1 7.3 6.9 8.6 14.5 10.7 0.04 0.05 7.2 8.6 8.1 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns ns ns ns ns ns ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z Delta LOW to HIGH Delta HIGH to LOW
Note: 1. Delays based on 35 pF loading.
v5.0
45
40MX and 42MX FPGA Families
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description Logic Module Propagation Delays1 tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q 1.2 1.3 1.2 1.2 1.3 1.4 1.4 1.6 1.5 1.6 1.6 1.8 1.8 1.9 1.8 2.1 2.5 2.7 2.6 2.9 ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
0.7 0.9 1.2 1.4 2.3
0.8 1.0 1.3 1.5 2.6
0.9 1.2 1.5 1.7 2.9
1.0 1.4 1.7 2.0 3.4
1.4 1.9 2.4 2.9 4.8
ns ns ns ns ns
Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
0.3 0.0 0.4 0.0 3.4 4.5 3.5 0.0 0.3 0.0 0.3 268
0.4 0.0 0.5 0.0 3.8 4.9 3.8 0.0 0.3 0.0 0.3 244
0.4 0.0 0.5 0.0 4.3 5.6 4.3 0.0 0.4 0.0 0.4 224
0.5 0.0 0.6 0.0 5.0 6.6 5.1 0.0 0.4 0.0 0.4 195
0.7 0.0 0.8 0.0 7.0 9.2 7.1 0.0 0.6 0.0 0.6 117
ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
46
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 4.75V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW 1.0 0.8 1.3 1.3 1.2 0.9 1.4 1.4 1.3 1.0 1.6 1.6 1.6 1.2 1.9 1.9 2.2 1.7 2.7 2.7 ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.0 2.3 2.5 2.8 3.7 2.2 2.5 2.8 3.1 4.1 2.5 2.9 3.2 3.5 4.7 3.0 3.4 3.7 4.1 5.5 4.2 4.7 5.2 5.7 7.7 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 2.3 2.2 3.4 3.7 296 268 1.2 1.3 1.2 1.3 0.3 0.3 0.0 0.0 2.6 2.4 3.7 4.1 269 244 2.4 2.7 3.5 3.9 1.4 1.5 1.4 1.5 0.3 0.3 0.0 0.0 3.0 3.3 4.0 4.5 247 224 2.7 3.0 3.9 4.3 1.5 1.7 1.5 1.7 0.4 0.4 0.0 0.0 3.5 3.9 4.7 5.2 215 195 3.0 3.4 4.4 4.9 1.8 2.0 1.8 2.0 0.5 0.5 0.0 0.0 4.9 5.5 7.8 8.6 129 117 3.6 4.0 5.2 5.7 2.5 2.7 2.5 2.7 0.6 0.6 5.0 5.5 7.3 8.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
47
40MX and 42MX FPGA Families
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
2.5 2.9 2.6 2.9 4.9 5.3 2.6 2.6 0.5 0.0 5.2 7.4 0.03 0.04 0.5 0.0
2.7 3.2 2.9 3.2 5.4 5.9 2.9 2.9 0.6 0.0 5.8 8.2 0.03 0.04
3.1 3.6 3.3 3.7 6.2 6.7 3.3 3.3 0.7 0.0 6.6 9.3 0.03 0.04
3.6 4.3 3.9 4.3 7.3 7.9 3.8 3.8 1.0 0.0 7.7 10.9 0.04 0.05
5.1 6.0 5.5 6.1 10.2 11.1 5.3 5.3
ns ns ns ns ns ns ns ns ns ns
10.8 15.3 0.06 0.07
ns ns ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW
2.4 2.9 2.7 2.9 4.9 5.3 4.2 4.2 0.5 0.0 5.2 7.4 0.03 0.04 0.5 0.0
2.7 3.2 2.9 3.2 5.4 5.9 4.6 4.6 0.6 0.0 5.8 8.2 0.03 0.04
3.1 3.6 3.3 3.7 6.2 6.7 5.2 5.2 0.7 0.0 6.6 9.3 0.03 0.04
3.6 4.3 3.9 4.3 7.3 7.9 6.1 6.1 1.0 0.0 7.7 10.9 0.04 0.05
5.1 6.0 5.5 6.1 10.2 11.1 8.6 8.6
ns ns ns ns ns ns ns ns ns ns
Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW
10.8 15.3 0.06 0.07
ns ns ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
48
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0C )
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2 1.0 1.3 1.6 1.9 3.2 1.1 1.4 1.8 2.1 3.6 1.2 1.6 2.0 2.4 4.1 1.4 1.9 2.4 2.9 4.8 2.0 2.7 3.3 4.0 6.7 ns ns ns ns ns
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.6 1.8 1.7 2.0
1.8 2.0 1.9 2.2
2.1 2.3 2.1 2.5
2.5 2.7 2.5 2.9
3.5 3.8 3.5 4.1
ns ns ns ns
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing 3, 4 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.5 0.0 0.6 0.0 4.7 6.2 5.0 0.0 0.3 0.0 0.3 161 0.5 0.0 0.6 0.0 5.3 6.9 5.6 0.0 0.3 0.0 0.3 146 0.6 0.0 0.7 0.0 6.0 7.8 6.2 0.0 0.3 0.0 0.3 135 0.7 0.0 0.8 0.0 7.0 9.2 7.1 0.0 0.4 0.0 0.4 117 0.9 0.0 1.2 0.0 9.8 12.9 9.9 0.0 0.6 0.0 0.6 70 ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
v5.0
49
40MX and 42MX FPGA Families
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 3.0V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW 1.5 1.2 1.8 1.8 1.6 1.3 2.0 2.0 1.8 1.4 2.3 2.3 2.17 1.7 2.7 2.7 3.0 2.4 3.7 3.7 ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.8 3.2 3.5 3.9 5.2 3.2 3.5 3.9 4.3 5.8 3.6 4.0 4.4 4.9 6.6 4.2 4.7 5.2 5.7 7.7 5.9 6.6 7.3 8.0 10.8 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 3.3 3.7 5.6 6.1 177 161 1.7 1.9 1.7 1.9 0.4 0.4 0.0 0.0 3.7 4.1 6.2 6.8 161 146 4.1 4.5 5.0 5.4 1.9 2.1 1.9 2.1 0.5 0.5 0.0 0.0 4.2 4.6 6.7 7.4 148 135 4.5 5.0 5.5 6.0 2.1 2.3 2.1 2.3 0.5 0.5 0.0 0.0 4.9 5.5 7.8 8.5 129 117 5.1 5.6 6.2 6.8 2.5 2.7 2.5 2.7 0.6 0.6 0.0 0.0 6.9 7.6 12.9 14.2 77 70 6.0 6.7 7.3 8.0 3.5 3.8 3.5 3.8 0.9 0.9 8.4 9.3 10.2 11.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
50
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
3.4 4.0 3.7 4.1 6.9 7.5 5.8 5.8 0.7 0.0 8.7 12.2 0.00 0.09 0.8 0.0
3.8 4.5 4.1 4.5 7.6 8.3 6.5 6.5 0.9 0.0 9.7 13.5 0.00 0.10
4.3 5.1 4.6 5.1 8.6 9.4 7.3 7.3 1.0 0.0 10.9 15.4 0.00 0.10
5.1 6.1 5.5 6.1 10.2 11.1 8.6 8.6 1.4 0.0 12.9 18.1 0.10 0.10
7.1 8.3 7.6 8.5 14.2 15.5 12.0 12.0
ns ns ns ns ns ns ns ns ns ns
18.0 25.3 0.01 0.10
ns ns ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW
3.4 4.1 3.7 4.1 6.9 7.5 5.8 5.8 0.7 0.0 8.7 12.2 0.04 0.05 0.8 0.0
3.8 4.5 4.1 4.5 7.6 8.3 6.5 6.5 0.9 0.0 9.7 13.5 0.04 0.05
5.5 4.2 4.6 5.1 8.6 9.4 7.3 7.3 1.0 0.0 10.9 15.4 0.05 0.06
6.4 5.0 5.5 6.1 10.2 11.1 8.6 8.6 1.4 0.0 12.9 18.1 0.06 0.07
9.0 7.0 7.6 8.5 14.2 15.5 12.0 12.0
ns ns ns ns ns ns ns ns ns ns
Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacity Loading, LOW to HIGH Capacity Loading, HIGH to LOW
18.0 25.3 0.08 0.10
ns ns ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
v5.0
51
40MX and 42MX FPGA Families
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 4. 75V, T J = 70 C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2 0.8 1.0 1.3 1.6 2.6 0.9 1.2 1.4 1.7 2.9 1.0 1.3 1.6 2.0 3.2 1.2 1.5 1.9 2.3 3.8 1.6 2.1 2.7 3.2 5.3 ns ns ns ns ns
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.4 1.4 1.4 1.6
1.5 1.6 1.5 1.7
1.7 1.8 1.7 2.0
2.0 2.1 2.0 2.3
2.8 3.0 2.8 3.3
ns ns ns ns
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3,4 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.3 0.0 0.7 0.0 3.4 4.5 6.8 0.0 0.5 0.0 0.5 215 0.4 0.0 0.8 0.0 3.8 5.0 7.6 0.0 0.5 0.0 0.5 1955 0.4 0.0 0.9 0.0 4.3 5.6 8.6 0.0 0.6 0.0 0.6 1795 0.5 0.0 1.0 0.0 5.0 6.6 10.1 0.0 0.7 0.0 0.7 1565 0.7 0.0 1.4 0.0 7.1 9.2 14.1 0.0 1.0 0.0 1.0 94 ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , point and position whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
52
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW 1.1 0.8 1.4 1.4 1.2 0.9 1.6 1.6 1.3 1.0 1.8 1.8 1.6 1.2 2.1 2.1 2.2 1.7 2.9 2.9 ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.8 2.1 2.3 2.6 3.6 2.0 2.3 2.6 3.0 4.0 2.3 2.6 3.0 3.3 4.6 2.7 3.1 3.5 3.9 5.4 4.0 4.3 4.9 5.4 7.5 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 3.2 3.7 3.2 3.7 0.3 0.3 0.0 0.0 2.8 3.2 4.2 4.6 237 215 0.0 0.0 3.1 3.5 4.67 5.1 215 195 2.6 2.9 3.8 4.5 3.5 4.1 3.5 4.1 0.4 0.4 0.0 0.0 5.5 4.0 5.1 5.6 198 179 2.9 3.2 4.2 5.0 4.0 4.59 4.0 4.6 0.4 0.4 0.0 0.0 4.1 4.7 5.8 6.4 172 156 3.3 3.6 4.8 5.6 4.7 5.4 4.7 5.4 0.5 0.5 0.0 0.0 5.7 6.6 9.7 10.7 103 94 3.9 4.3 5.6 6.6 6.6 7.6 6.6 7.6 0.7 0.7 5.4 6.0 7.8 9.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Minimum Pulse Width LOW FO = 32 FO = 384 Maximum Skew FO = 32 FO = 384
Input Latch External Set-Up FO = 32 FO = 384 Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
53
40MX and 42MX FPGA Families
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 2.5 3.0 2.7 3.0 5.4 5.0 2.9 2.9 5.7 8.0 0.03 0.04 2.8 3.3 3.0 3.3 6.0 5.6 3.2 3.2 6.3 8.9 0.03 0.04 3.2 3.7 3.4 3.8 6.8 6.3 3.6 3.6 7.1 10.1 0.03 0.04 3.7 4.4 4.0 4.4 8.0 7.4 4.3 4.3 8.4 11.9 0.04 0.05 5.2 6.1 5.6 6.2 11.2 10.4 6.0 6.0 11.9 16.7 0.06 0.07 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 3.2 2.5 2.7 3.0 5.4 5.0 5.1 5.1 5.7 8.0 0.03 0.04 3.6 2.7 3.0 3.3 6.0 5.6 5.6 5.6 6.3 8.9 0.03 0.04 4.0 3.1 3.4 3.8 6.8 6.3 6.4 6.4 7.1 10.1 0.03 0.04 4.7 3.6 4.0 4.4 8.0 7.4 7.5 7.5 8.4 11.9 0.04 0.05 6.6 5.1 5.6 6.2 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
54
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0C )
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tCO tGO tRS Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2 1.1 1.5 1.8 2.2 3.6 1.2 1.6 2.0 2.4 4.0 1.4 1.8 2.3 2.7 4.5 1.6 2.1 2.7 3.2 5.3 2.3 3.0 3.8 4.5 7.5 ns ns ns ns ns
1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.9 2.0 1.9 2.2
2.1 2.2 2.1 2.4
2.4 2.5 2.4 2.8
2.8 3.0 2.8 3.3
4.0 4.2 4.0 4.6
ns ns ns ns
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3, 4 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 0.5 0.0 1.0 0.0 4.8 6.2 9.5 0.0 0.7 0.0 0.7 129 0.5 0.0 1.1 0.0 5.3 6.9 10.6 0.0 0.8 0.0 0.8 117 0.6 0.0 1.2 0.0 6.0 7.9 12.0 0.0 0.9 0.0 0.89 108 0.7 0.0 1.4 0.0 7.1 9.2 14.1 0.0 1.01 0.0 1.01 94 0.9 0.0 2.0 0.0 9.9 12.9 19.8 0.0 1.4 0.0 1.4 56 ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
v5.0
55
40MX and 42MX FPGA Families
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y LOW G to Y HIGH G to Y LOW 1.5 1.1 2.0 2.0 1.6 1.3 2.2 2.2 1.9 1.4 2.5 2.5 2.2 1.7 2.9 2.9 3.1 2.4 4.1 4.1 ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.6 2.9 3.3 3.6 5.1 2.9 3.2 3.6 4.0 5.6 3.2 3.7 4.1 4.6 6.4 3.8 4.3 4.9 5.4 7.5 5.3 6.1 6.8 7.6 10.5 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Input Latch External Set-Up FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 3.9 4.5 7.0 7.7 142 129 5.7 6.6 5.3 6.2 0.5 2.2 0.0 0.0 4.3 4.9 7.8 8.6 129 117 4.4 4.8 5.3 6.2 6.3 7.4 5.9 6.9 0.5 2.4 0.0 0.0 4.9 5.6 8.4 9.3 119 108 4.8 5.3 5.9 6.9 7.1 8.3 6.7 7.9 0.6 2.7 0.0 0.0 5.7 6.6 9.7 10.7 103 94 5.5 6.0 6.7 7.9 8.4 9.8 7.8 9.2 0.7 3.2 0.0 0.0 8.0 9.2 16.2 17.8 62 56 6.5 7.1 7.8 9.2 11.8 13.7 11.0 12.9 1.0 4.5 9.0 9.9 11.0 12.9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Input Latch External Hold FO = 32 FO = 384 Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
56
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 3.5 4.1 3.8 4.2 7.6 7.0 4.8 4.8 8.0 3.9 4.6 4.2 4.6 8.4 7.8 5.3 5.3 8.9 4.4 5.2 4.8 5.3 9.5 8.8 6.0 6.0 10.1 14.2 0.05 0.06 5.2 6.1 5.6 6.2 11.2 10.4 7.2 7.2 11.9 16.7 0.06 0.07 7.3 8.6 7.8 8.7 15.7 14.5 10.0 10.0 16.7 23.3 0.08 0.10 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
11.3 0.04 0.05
12.5 0.04 0.05
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 4.5 3.4 3.8 4.2 7.6 7.0 7.1 7.1 8.0 11.3 0.04 0.05 5.0 3.8 4.2 4.6 8.4 7.8 7.9 7.9 8.9 12.5 0.04 0.05 5.6 4.3 4.8 5.3 9.5 8.8 8.9 8.9 10.1 14.2 0.05 0.06 6.6 5.1 5.6 6.2 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 9.3 7.1 7.8 8.7 15.7 14.5 14.7 14.7 16.7 23.3 0.08 0.10 ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
v5.0
57
40MX and 42MX FPGA Families
A 42 M X2 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 4. 75V, T J = 70 C)
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay
2 1
`-2'Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.2 1.4
1.3 1.6
1.5 1.8
1.8 2.1
2.5 3.0
ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
0.8 1.0 1.3 1.5 2.4
0.9 1.2 1.4 1.7 2.7
1.0 1.3 1.6 1.9 3.0
1.2 1.5 1.9 2.2 3.6
1.7 2.1 2.6 3.1 5.0
ns ns ns ns ns
Logic Module Sequential Timing tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.4 0.0 3.3 4.4 0.3 0.0
1.3 1.2 0.4 0.0 1.4 0.5 0.0 3.7 4.8
1.4 1.3 0.4 0.0 1.6 0.5 0.0 4.2 5.3
1.6 1.5 0.5 0.0 1.8 0.6 0.0 4.9 6.5
1.9 1.8 0.7 0.0 2.1 0.8 0.0 6.9 9.0
2.7 2.5
ns ns ns ns
2.9
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
58
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.5 4.7 1.0 1.3 0.0 0.5 5.2 1.1 1.4 0.0 0.6 5.9 1.3 1.6 0.0 0.7 6.9 1.5 1.9 0.0 1.0 9.7 2.1 2.6 ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.8 2.1 2.3 2.5 3.4 2.0 2.3 2.5 2.8 3.8 2.3 2.6 2.9 3.2 4.3 2.7 3.1 3.4 3.7 5.1 3.8 4.3 4.8 5.2 7.1 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW FO=32 FO=486 FO=32 FO=486 2.2 2.4 2.2 2.4 0.5 0.5 0.0 0.0 2.8 3.3 4.7 5.1 210 193 0.0 0.0 3.1 3.7 5.2 5.7 191 175 2.6 2.9 3.7 4.3 2.4 2.6 2.4 2.6 0.6 0.6 0.0 0.0 3.5 4.2 5.7 6.2 176 161 2.9 3.2 4.1 4.7 2.7 3.0 2.7 3.0 0.7 0.7 0.0 0.0 4.1 4.9 6.5 7.1 153 140 3.3 3.6 4.6 5.4 3.2 3.5 3.2 3.5 0.8 0.8 0.0 0.0 5.7 6.9 10.9 11.9 92 84 3.9 4.3 5.4 6.3 4.5 4.9 4.5 4.9 1.1 1.1 5.4 5.9 7.6 8.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Minimum Pulse Width HIGH FO=32 FO=486 Minimum Pulse Width LOW FO=32 FO=486 Maximum Skew FO=32 FO=486
Input Latch External Set-Up FO=32 FO=486 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
59
40MX and 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 5.6 2.4 2.8 2.5 2.8 5.2 4.8 2.9 2.9 0.5 0.0 6.1 2.7 3.2 2.8 3.1 5.7 5.3 3.2 3.2 0.6 0.0 6.9 3.1 3.6 3.2 3.5 6.5 6.0 3.6 3.6 0.7 0.0 8.1 3.6 4.2 3.8 4.2 7.6 7.1 4.3 4.3 1.0 0.0 11.4 5.1 5.9 5.3 5.9 10.7 9.9 6.0 6.0 ns ns ns ns ns ns ns ns ns ns ns Min. Max. `-2'Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
22.0 0.07 0.06
ns ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 5.5 3.1 2.4 2.5 2.8 5.2 4.8 4.9 4.9 0.5 0.0 6.1 3.5 2.6 2.8 3.1 5.7 5.3 5.4 5.4 0.6 0.0 6.9 3.9 3.0 3.2 3.5 6.5 6.0 6.2 6.2 0.7 0.0 8.1 4.6 3.5 3.8 4.2 7.6 7.1 7.2 7.2 1.0 0.0 11.3 6.4 4.9 5.3 5.8 10.7 9.9 10.1 10.1 ns ns ns ns ns ns ns ns ns ns ns
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
22.0 0.07 0.06
ns ns/pF ns/pF
dTLH dTHL
Note: 1. Delays based on 35 pF loading.
60
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X2 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0C )
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay
2 1
`-2'Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
2.0 1.1
1.8 2.2
2.1 2.5
2.5 3.0
3.4 4.2
ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
1.7 2.0 1.1 1.5 1.8
1.3 1.6 2.0 2.3 3.7
1.4 1.8 2.2 2.6 4.2
1.7 2.1 2.6 3.1 5.0
2.3 3.0 3.7 4.3 7.0
ns ns ns ns ns
Logic Module Sequential Timing tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.6 0.0 4.6 6.1 0.4 0.0
2.1 3.4 0.5 0.0 2.0 0.6 0.0 5.2 6.8
2.0 1.9 0.6 0.0 2.2 0.7 0.0 5.8 7.7
2.3 2.1 0.7 0.0 2.5 0.8 0.0 6.9 9.0
2.7 2.5 0.9 0.0 2.9 1.2 0.0 9.6 12.6
3.7 3.4
ns ns ns ns
4.1
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
v5.0
61
40MX and 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.7 6.5 1.4 1.8 0.0 0.7 7.3 1.6 1.9 0.0 0.8 8.2 1.8 2.2 0.0 1.0 9.7 2.2 2.6 0.0 1.4 13.5 3.0 3.6 ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.6 2.9 3.2 3.5 4.8 2.9 3.2 3.6 3.9 5.3 3.2 3.6 4.0 4.4 6.1 3.8 4.3 4.8 5.2 7.1 5.3 6.0 6.6 7.3 10.0 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input LOW to HIGH Input HIGH to LOW FO=32 FO=486 FO=32 FO=486 3.0 3.3 3.0 3.3 0.8 0.8 0.0 0.0 3.9 4.6 7.8 8.6 126 116 0.0 0.0 4.3 5.2 8.7 9.5 115 105 4.4 4.8 5.1 6.0 3.3 3.7 3.4 3.7 0.8 0.8 0.0 0.0 4.9 5.8 9.47 10.4 106 97 4.8 5.3 5.7 6.6 3.8 4.2 3.8 4.2 1.0 1.0 0.0 0.0 5.7 6.9 10.8 11.9 92 84 5.5 6.0 6.4 7.5 4.5 4.9 4.5 4.9 1.1 1.1 0.0 0.0 8.1 9.6 18.2 19.9 55 50 6.5 7.1 7.6 8.8 6.3 6.9 6.3 6.9 1.6 1.6 9.1 10.0 10.6 12.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Minimum Pulse Width HIGH FO=32 FO=486 Minimum Pulse Width LOW FO=32 FO=486 Maximum Skew FO=32 FO=486
Input Latch External Set-Up FO=32 FO=486 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
62
v5.0
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A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3 Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.7 0.0 7.67 3.4 4.0 3.6 3.9 7.2 6.7 4.8 4.8 0.7 0.0 8.5 3.8 4.4 4.0 4.4 8.0 7.5 5.3 5.3 0.8 0.0 9.6 4.3 5.0 4.5 5.0 9.07 8.5 6.0 6.0 1.0 0.0 11.3 5.0 5.9 5.3 5.8 10.7 9.9 7.2 7.2 1.4 0.0 15.9 7.1 8.3 7.4 8.2 14.9 13.9 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
22.0 0.07 0.06
30.8 0.10 0.08
ns ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.7 0.0 7.7 4.8 3.5 3.6 3.4 7.2 6.7 6.8 6.8 0.7 0.0 8.5 5.3 3.9 4.0 4.0 8.0 7.5 7.6 7.6 0.8 0.0 9.6 5.5 4.1 4.5 5.0 9.01 8.5 8.6 8.6 1.0 0.0 11.3 6.4 4.9 5.3 5.8 10.7 9.9 10.1 10.1 1.4 0.0 15.9 9.0 6.8 7.4 8.2 14.9 13.9 14.2 14.2 ns ns ns ns ns ns ns ns ns ns ns
tACO
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
22.0 0.07 0.06
30.8 0.10 0.08
ns ns/pF ns/pF
dTLH dTHL
Note: 1. Delays based on 35 pF loading.
v5.0
63
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 4. 75V, T J = 70 C)
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay
2 1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.3 1.6
1.5 1.8
1.7 2.0
2.0 2.4
2.7 3.3
ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
0.9 1.3 1.6 2.0 3.3 0.3
1.0 1.4 1.8 2.2 3.7 0.4
1.2 1.6 2.0 2.5 4.2 0.4
1.4 1.9 2.4 2.9 4.9 0.5
2.0 2.7 3.4 4.1 6.9 0.7
ns ns ns ns ns ns
Decode-to-Output Routing Delay
3, 4
Logic Module Sequential Timing tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.7 0.0 3.3 4.4 0.3 0.0
1.3 1.3 0.34 0.0 1.6 0.8 0.0 3.7 4.8
1.4 1.4 0.4 0.0 1.7 0.9 0.0 4.2 5.5
1.6 1.6 0.5 0.0 2.0 1.0 0.0 4.9 6.4
1.9 1.9 0.7 0.0 2.3 1.4 0.0 6.9 9.0
2.7 2.7
ns ns ns ns
3.2
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
64
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
Logic Module Timing Parameter Description Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 1.6 0.0 0.6 3.4 2.7 0.0 2.8 0.0 6.8 6.8 3.4 3.4 1.8 0.0 0.7 3.8 3.0 0.0 3.1 0.0 7.5 7.5 3.8 3.78 2.0 0.0 0.8 4.3 3.4 0.0 3.5 0.0 8.5 8.5 4.3 4.3 2.4 0.0 0.9 5.0 4.0 0.0 4.1 0.0 10.0 10.0 5.0 5.0 3.4 0.0 1.3 7.0 5.6 0.0 5.7 0.0 14.0 14.0 7.0 7.0 ns ns ns ns ns ns ns ns ns ns ns ns `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 8.8 1.6 0.0 0.6 3.4 2.7 0.0 1.2 8.1 9.8 1.8 0.0 0.7 3.8 3.0 0.0 1.34 9.0 11.1 2.0 0.0 0.8 4.3 3.4 0.0 1.5 10.2 13.0 2.4 0.0 0.9 5.0 4.0 0.0 1.8 12.0 18.2 3.4 0.0 1.3 7.0 5.6 0.0 2.5 16.8 ns ns ns ns ns ns ns ns ns
v5.0
65
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.5 4.7 1.0 1.4 0.0 0.5 5.2 1.1 1.6 0.0 0.6 5.9 1.3 1.8 0.0 0.7 6.9 1.5 2.1 0.0 1.0 9.7 2.1 2.9 ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.0 2.3 2.6 3.0 4.3 2.2 2.6 2.9 3.3 4.8 2.5 2.9 3.3 3.8 5.5 2.9 3.4 3.9 4.4 6.4 4.1 4.8 5.5 6.2 9.0 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input LOW to HIGH Input HIGH to LOW FO=32 FO=635 FO=32 FO=635 1.8 2.0 1.8 2.0 0.8 0.8 0.0 0.0 2.8 3.3 5.5 6.0 180 166 0.0 0.0 3.2 3.7 6.1 6.6 164 151 2.7 3.0 3.8 4.9 2.0 2.2 2.0 2.2 0.8 0.8 0.0 0.0 3.6 4.2 6.6 7.2 151 139 3.0 3.3 4.2 5.4 2.2 2.5 2.2 2.5 0.9 0.9 0.0 0.0 4.2 4.9 7.6 8.3 131 121 3.4 3.8 4.8 6.1 2.6 2.9 2.6 2.9 1.0 1.0 0.0 0.0 5.9 6.9 12.7 13.8 79 73 4.0 4.4 5.6 7.2 3.6 4.1 3.6 4.1 1.4 1.4 5.6 6.2 7.8 10.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Minimum Pulse Width HIGH FO=32 FO=635 Minimum Pulse Width LOW FO=32 FO=635 Maximum Skew FO=32 FO=635
Input Latch External Set-Up FO=32 FO=635 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
66
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A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 4.75V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 5.7 2.6 3.0 2.7 3.0 5.3 4.9 2.9 2.9 0.5 0.0 6.3 2.8 3.3 3.0 3.3 5.8 5.5 3.3 3.3 0.6 0.0 7.1 3.2 3.7 3.3 3.7 6.6 6.2 3.7 3.7 0.7 0.0 8.4 3.8 4.4 3.9 4.3 7.8 7.3 4.4 4.4 1.0 0.0 11.8 5.3 6.2 5.5 6.1 10.9 10.2 6.1 6.1 ns ns ns ns ns ns ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
7.8 0.07 0.07
8.6 0.08 0.08
9.8 0.09 0.09
11.5 0.10 0.10
16.1 0.14 0.14
ns ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0 5.7 3.5 2.5 2.7 2.9 5.3 4.9 5.0 5.0 0.5 0.0 6.3 3.9 2.7 3.0 3.3 5.8 5.5 5.6 5.6 0.6 0.0 7.1 4.5 3.1 3.3 3.7 6.6 6.2 6.3 6.3 0.7 0.0 8.4 5.2 3.6 3.9 4.3 7.8 7.3 7.5 7.5 1.0 0.0 11.8 7.3 5.1 5.5 6.1 10.9 10.2 10.4 10.4 ns ns ns ns ns ns ns ns ns ns ns
tACO
7.78 0.07 0.07
8.6 0.08 0.08
9.8 0.09 0.09
11.5 0.10 0.10
16.1 0.14 0.14
ns ns/pF ns/pF
dTLH dTHL
Note: 1. Delays based on 35 pF loading.
v5.0
67
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0C )
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPD tPDD Internal Array Module Delay Internal Decode Module Delay
2 1
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
1.9 2.2
2.1 2.5
2.3 2.8
2.7 3.3
3.8 4.7
ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.3 1.8 2.3 2.8 4.6 0.5
1.5 2.0 2.5 3.1 5.2 0.5
1.7 2.3 2.8 3.5 5.8 0.6
2.0 2.7 3.4 4.1 6.9 0.7
2.7 3.7 4.7 5.7 9.6 1.0
ns ns ns ns ns ns
Decode-to-Output Routing Delay
3, 4
Logic Module Sequential Timing tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 1.0 0.0 4.6 6.1 0.4 0.0
1.8 1.8 0.5 0.0 2.2 1.1 0.0 5.2 6.8
2.0 2.0 0.6 0.0 2.4 1.2 0.0 5.8 7.7
2.3 2.3 0.7 0.0 2.7 1.4 0.0 6.9 9.0
2.7 2.7 0.9 0.0 3.2 2.0 0.0 9.6 12.6
3.7 3.7
ns ns ns ns
4.5
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
68
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
Logic Module Timing Parameter Description Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 2.3 0.0 0.9 4.8 3.8 0.0 3.9 0.0 9.5 9.5 4.8 4.8 2.5 0.0 1.0 5.3 4.2 0.0 4.3 0.0 10.5 10.5 5.3 5.3 2.8 0.0 1.1 6.0 4.8 0.0 4.9 0.0 11.9 11.9 6.0 6.0 3.4 0.0 1.3 7.0 5.6 0.0 5.7 0.0 14.0 14.0 7.0 7.0 4.8 0.0 1.8 9.8 7.8 0.0 8.0 0.0 19.6 19.6 9.8 9.8 ns ns ns ns ns ns ns ns ns ns ns ns `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 12.3 2.3 0.0 0.9 4.8 3.8 0.0 1.8 11.3 13.7 2.5 0.0 1.0 5.3 4.2 0.0 2.0 12.6 15.5 2.8 0.0 1.1 6.0 4.8 0.0 2.1 14.3 18.2 3.4 0.0 1.3 7.0 5.6 0.0 2.5 16.8 25.5 4.8 0.0 1.8 9.8 7.8 0.0 3.5 23.5 ns ns ns ns ns ns ns ns ns
v5.0
69
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.7 6.5 1.4 2.0 0.0 0.7 7.3 1.6 2.2 0.0 0.8 8.2 1.8 2.5 0.0 1.0 9.7 2.1 2.9 0.0 1.4 13.5 3.0 4.1 ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.8 3.2 3.7 4.2 6.1 3.1 3.5 4.1 4.6 6.8 3.5 4.1 4.7 5.3 7.7 4.07 4.8 5.5 6.2 9.0 5.7 6.7 7.7 8.7 12.6 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input LOW to HIGH Input HIGH to LOW FO=32 FO=635 FO=32 FO=635 2.5 2.8 2.5 2.8 1.0 1.0 0.0 0.0 4.0 4.6 9.2 9.9 108 100 0.0 0.0 4.4 5.2 10.2 11.0 98 91 4.6 5.0 5.3 6.8 2.7 3.1 2.7 3.1 1.2 1.2 0.0 0.0 5.0 5.9 11.1 12.0 90 83 5.1 5.6 5.9 7.6 3.1 3.5 3.1 3.5 1.3 1.3 0.0 0.0 5.9 6.9 12.7 13.8 79 73 5.7 6.3 6.7 8.6 3.6 4.1 3.6 4.1 1.5 1.5 0.0 0.0 8.2 9.6 21.2 23.0 47 44 6.7 7.4 7.8 10.1 5.1 5.7 5.1 5.7 2.2 2.2 9.3 10.3 11.0 14.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Minimum Pulse Width HIGH FO=32 FO=635 Minimum Pulse Width LOW FO=32 FO=635 Maximum Skew FO=32 FO=635
Input Latch External Set-Up FO=32 FO=635 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
70
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 3.0V, T J = 70C)
`-3' Speed Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.7 0.0 7.9 3.6 4.2 3.7 4.1 7.34 6.9 4.9 4.9 0.7 0.0 8.8 4.0 4.6 4.2 4.6 8.2 7.6 5.5 5.5 0.8 0.0 10.0 4.5 5.2 4.7 5.2 9.3 8.7 6.2 6.2 1.0 0.0 11.8 5.3 6.2 5.5 6.1 10.9 10.2 7.3 7.3 1.4 0.0 16.5 7.4 8.6 7.7 8.5 15.3 14.3 10.2 10.2 ns ns ns ns ns ns ns ns ns ns ns Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
10.9 0.10 0.10
12.1 0.11 0.11
13.7 0.12 0.12
16.1 0.14 0.14
22.5 0.20 0.20
ns ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.7 0.0 7.9 4.9 3.4 3.7 4.1 7.4 6.9 7.0 7.0 0.7 0.0 8.8 5.5 3.8 4.1 4.6 8.2 7.6 7.8 7.8 0.8 0.0 10.0 6.2 4.3 4.7 5.2 9.3 8.7 8.9 8.9 1.0 0.0 11.8 7.3 5.1 5.5 6.1 10.9 10.2 10.4 10.4 1.4 0.0 16.5 10.3 7.1 7.7 8.5 15.3 14.3 14.6 14.6 ns ns ns ns ns ns ns ns ns ns ns
tACO
10.9 0.10 0.10
12.1 0.11 0.11
13.7 0.12 0.12
16.1 0.14 0.14
22.5 0.20 0.20
ns ns/pF ns/pF
dTLH dTHL
Note: 1. Delays based on 35 pF loading.
v5.0
71
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5V, T J = 125 C )
`-2' Speed Parameter Description
1
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Combinatorial Functions tPD tPDD
Internal Array Module Delay Internal Decode Module Delay
2
1.5 1.8
1.7 2.0
2.0 2.4
2.7 3.3
ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.0 1.4 1.8 2.2 3.7 0.4
1.2 1.6 2.0 2.5 4.2 0.4
1.4 1.9 2.4 2.9 4.9 0.5
2.0 2.7 3.4 4.1 6.9 0.7
ns ns ns ns ns ns
Decode-to-Output Routing Delay
3, 4
Logic Module Sequential Timing tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.8 0.0 3.7 4.8 0.4 0.0
1.4 1.4 0.4 0.0 1.7 0.9 0.0 4.2 5.5
1.6 1.6 0.5 0.0 2.0 1.0 0.0 4.9 6.4
1.9 1.9 0.7 0.0 2.3 1.4 0.0 6.9 9.0
2.7 2.7
ns ns ns ns
3.2
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
72
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125C)
Logic Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 1.8 0.0 0.7 3.8 3.0 0.0 3.1 0.0 7.5 7.5 3.8 3.8 2.0 0.0 0.8 4.3 3.4 0.0 3.5 0.0 8.5 8.5 4.3 4.3 2.4 0.0 0.9 5.0 4.0 0.0 4.1 0.0 10.0 10.0 5.0 5.0 3.4 0.0 1.3 7.0 5.6 0.0 5.7 0.0 14.0 14.0 7.0 7.0 ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 9.8 1.8 0.0 0.7 3.8 3.0 0.0 1.4 9.0 11.1 2.1 0.0 0.8 4.3 3.4 0.0 1.5 10.2 13.0 2.4 0.0 0.9 5.0 4.0 0.0 1.8 12.0 18.2 3.4 0.0 1.3 7.0 5.6 0.0 2.5 16.8 ns ns ns ns ns ns ns ns ns
v5.0
73
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.5 5.2 1.1 1.6 0.0 0.6 5.9 1.3 1.8 0.0 0.7 6.9 1.5 2.1 0.0 1.0 9.7 2.1 2.9 ns ns ns ns ns
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 2.2 2.6 2.9 3.3 4.8 2.5 2.9 3.3 3.8 5.5 2.9 3.4 3.9 4.4 6.4 4.1 4.8 5.5 6.2 9.0 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 3.2 3.7 6.1 6.6 164 151 2.0 2.2 2.0 2.2 0.8 0.8 0.0 0.0 3.6 4.2 6.6 7.2 151 139 3.0 3.3 4.2 5.4 2.2 2.5 2.2 2.5 0.9 0.9 0.0 0.0 4.2 4.9 7.6 8.3 131 121 3.4 3.8 4.8 6.1 2.6 2.9 2.6 2.9 1.0 1.0 0.0 0.0 5.9 6.9 12.7 13.8 79 73 4.0 4.4 5.6 7.2 3.7 4.1 3.7 4.1 1.4 1.4 5.6 6.2 7.8 10.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Maximum Datapath Frequency
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
74
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4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW
1
2.8 3.3 3.0 3.3 5.8 5.5 3.3 3.3 0.5 0.0 6.3 8.6 0.08 0.08 0.6 0.0
3.2 3.7 3.3 3.7 6.6 6.2 3.7 3.7 0.7 0.0 7.1 9.8 0.09 0.09
3.8 4.4 3.9 4.3 7.8 7.3 4.4 4.4 1.0 0.0 8.4 11.5 0.10 0.10
5.3 6.2 5.5 6.1 11.0 10.2 6.1 6.1
ns ns ns ns ns ns ns ns ns ns
11.8 16.1 0.14 0.14
ns ns ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.5 0.0
3.9 2.7 3.0 3.3 5.8 5.5 5.6 5.6 0.6 0.0 6.3 8.6 0.08 0.08
4.5 3.1 3.3 3.7 6.6 6.2 6.3 6.3 0.7 0.0 7.1 9.78 0.09 0.09
5.2 3.7 3.9 4.3 7.8 7.3 7.5 7.5 1.0 0.0 8.4 11.5 0.10 0.10
7.3 5.1 5.5 6.1 10.9 10.2 10.4 10.4
ns ns ns ns ns ns ns ns ns ns
11.8 16.1 0.14 0.14
ns ns ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
v5.0
75
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 3.0V, T J = 125 C )
`-2' Speed Parameter Description
1
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Combinatorial Functions tPD tPDD Internal Array Module Delay
2.4 2.9
2.7 3.3
3.2 3.9
ns ns
Internal Decode Module Delay
2
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.7 2.3 2.9 3.6 6.0 6.7
2.0 2.6 3.3 4.0 6.8 0.8
2.3 3.1 3.9 4.7 8.0 0.9
ns ns ns ns ns ns
Decode-to-Output Routing Delay
3, 4
Logic Module Sequential Timing tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 1.3 0.0 6.0 7.9 0.6 0.0
2.4 2.4 0.7 0.0 2.9 1.4 0.0 6.8 8.9
2.7 2.7 0.8 0.0 3.2 1.7 0.0 8.0 10.5
3.1 3.1
ns ns ns ns
3.8
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 2. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 3. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
76
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 3.0V, T J = 125C)
Logic Module Timing Parameter Description `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units
Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 6.1 4.8 0.0 4.9 0.0 2.9 0.0 12.1 12.1 6.1 6.2 3.2 0.0 1.2 6.9 5.5 0.0 5.6 0.0 13.8 13.8 6.9 7.0 3.9 0.0 1.5 8.1 6.4 0.0 6.6 0.0 16.2 16.2 8.1 8.2 ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up to Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Out Hold Time 15.9 2.9 0.0 1.1 6.1 4.8 0.0 2.4 14.7 18.0 3.2 0.0 1.2 6.9 5.5 0.0 2.5 16.6 21.1 3.9 0.0 1.5 8.1 6.4 0.0 2.9 19.5 ns ns ns ns ns ns ns ns ns
v5.0
77
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 3.0V, T J = 125C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 0.0 0.8 8.4 1.9 2.6 0.0 0.9 9.5 2.1 2.9 0.0 1.1 11.2 2.5 3.4 ns ns ns ns ns
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3.6 4.2 4.8 5.4 7.9 4.0 4.7 5.4 6.1 8.9 4.8 5.6 6.4 7.2 10.5 ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input LOW to HIGH Input HIGH to LOW Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 5.1 5.9 11.8 12.7 85 78 3.1 3.5 3.1 3.5 1.4 1.4 0.0 0.0 5.8 6.7 12.8 13.8 78 71 5.9 6.5 6.9 8.8 3.5 4.0 3.5 4.0 1.6 1.6 0.0 0.0 6.8 7.9 14.7 15.9 67 62 6.7 7.3 7.8 10.0 4.2 4.7 4.2 4.7 1.8 1.8 7.8 8.6 9.1 11.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
78
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 3.0V, T J = 125C)
`-2' Speed Parameter Description Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. Units
TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Output Set-Up I/O Latch Output Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW
1
4.6 5.3 4.8 5.3 9.5 8.9 6.3 6.3 0.8 0.0 10.2 14.0 0.13 0.13 0.9 0.0
5.2 6.1 5.4 6.0 10.8 10.0 7.2 7.2 1.1 0.0 11.6 15.9 0.14 0.14
6.2 7.2 6.4 7.1 12.7 11.8 8.4 8.4
ns ns ns ns ns ns ns ns ns ns
13.7 18.7 0.16 0.16
ns ns ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL
Data-to-Pad HIGH Data-to-Pad LOW Enable Pad Z to HIGH Enable Pad Z to LOW Enable Pad HIGH to Z Enable Pad LOW to Z G-to-Pad HIGH G-to-Pad LOW I/O Latch Set-Up I/O Latch Hold I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O Capacitive Loading, LOW to HIGH Capacitive Loading, HIGH to LOW 0.8 0.0
6.4 4.5 4.8 5.3 9.5 8.9 9.1 9.1 0.9 0.0 10.2 14.0 0.13 0.13
7.3 5.1 5.5 6.0 10.8 10.0 10.3 10.3 1.1 0.0 13.7 18.7 0.16 0.16
8.5 5.9 6.4 7.1 12.7 11.8 12.1 12.1
ns ns ns ns ns ns ns ns ns ns
13.7 18.7 0.16 0.16
ns ns ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
v5.0
79
40MX and 42MX FPGA Families
Pi n D es c r i pt i on s
CLK, CLKA, CLKB Global Clock (Input)
accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
QCLKA,B,C,D Quadrant Clock (Input/Output)
TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
DCLK Diagnostic Clock (Input)
Quadrant clock inputs. When not used as a register control signal, these pins can function as general-purpose I/Os.
SDI Serial Data Input (Input)
TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
GND Ground (Input)
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDO, TDO, I/O Serial Data (Output)
Input LOW supply voltage.
I/O Input/Output (Input, Output)
Input, output, tri-state, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the Designer Series software.
LP Low Power Mode
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is not available for 40MX devices.
TCK Test Clock
Controls the low power mode of all 42MX devices. This pin must be set HIGH to switch the device to low power mode. To exit the LOW power mode, the LP pin must be set LOW.
MODE Mode (Input)
Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O when the test fuse is not programmed. BST pins are only available in the A42MX24, A42MX24A, and A42MX36 devices.
TDI Test Data In
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). To provide verification capability, the MODE pin should be held HIGH. To facilitate this, the MODE pin should be terminated to GND through a 10K3/4 resistor so that the MODE pin can be pulled HIGH when required.
NC No Connection
Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin functions as an I/O when the test fuse is not programmed. BST pins are only available in the A42MX24 and A42MX36 devices.
TDO Test Data Out
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
PRA, I/O Probe A (Output)
Serial data output for BST instructions and test data. This pin functions as an I/O when the test fuse is not programmed. BST pins are only available in the A42MX24 and A42MX36 devices.
TMS Test Mode Select
The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
PRB, I/O Probe B (Output)
Serial data input for boundary scan test mode. Data is shifted in on the rising edge of TCK. This pin functions as an I/O when the test fuse is not programmed. BST pins are only available in the A42MX24 and A42MX36 devices.
VCC Supply Voltage (Input)
Input HIGH supply voltage.
V C CA Supply Voltage (Input)
Input HIGH supply voltage, supplies array core only.
V C CI Supply Voltage (Input)
Input HIGH supply voltage, supplies I/O cells only.
WD Wide Decode Output
The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is
80
When a wide decode module is used in a 42MX device, this pin can be used as a dedicated output from the wide decode module. This direct connection eliminates additional interconnect delays associated with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type to the output of the wide decode macro and place this output on one of the reserved WD pins.
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s
44-Pin PLCC
1 44
44-Pin PLCC
44- pin P LCC
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A40MX02 Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O VCC I/O I/O I/O I/O GND I/O
A40MX04 Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O VCC I/O I/O I/O I/O GND I/O
Pin Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A40MX02 Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O GND I/O
A40MX04 Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O GND I/O
v5.0
81
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s
68-Pin PLCC
1 68
68-Pin PLCC
68- Pi n PL CC
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
A40MX02 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC I/O I/O
A40MX04 Function I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC I/O I/O
Pin Number 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
A40MX02 Function I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O
A40MX04 Function I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
A40MX02 Function I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O
A40MX04 Function I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O
82
v5.0
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Pa c ka ge P i n A s si g nm e n t s (continued)
84-Pin PLCC
1
84
84-Pin PLCC
v5.0
83
40MX and 42MX FPGA Families
84- Pi n PL CC
Pin A40MX04 A42MX09 A42MX16 A42MX24 Number Function Function Function Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O (WD) GND I/O I/O (WD) I/O (WD) I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O TMS, I/O TDI, I/O I/O (WD) I/O I/O (WD) I/O (WD) I/O I/O I/O
Pin A40MX04 A42MX09 A42MX16 Number Function Function Function 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLK, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O SDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND (LP) VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O PRA, I/O I/O VCCA VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND (LP) VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O PRA, I/O I/O VCCA
A42MX24 Function VCCA I/O (WD) I/O (WD) I/O (WD) I/O (WD) I/O GND I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O GND (LP) VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDI, I/O I/O I/O (WD) I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O VCCA
CLKB, I/O CLKB, I/O CLKB, I/O
DCLK, I/O DCLK, I/O DCLK, I/O
SDO, I/O SDO, TDO (WD)
CLKA, I/O CLKA, I/O
84
v5.0
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Pa c ka ge P i n A s si g nm e n t s (continued)
100-Pin PQFP Package (Top View)
100-Pin PQFP
100 1
v5.0
85
40MX and 42MX FPGA Families
100- P in P Q FP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function NC NC NC NC NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC NC I/O I/O GND GND I/O I/O NC NC NC NC NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O
Pin Number 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function I/O I/O I/O VCC VCC I/O I/O I/O NC NC NC NC NC NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O NC NC NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O NC NC VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
DCLK, I/O DCLK, I/O I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O
GND (LP) GND (LP) VCCA VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
86
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
100- P in P Q FP (C ont inu ed)
Pin Number 79 80 81 82 83 84 85 86 87 88 89
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function NC NC NC NC I/O I/O I/O GND GND I/O I/O NC I/O I/O I/O I/O I/O I/O GND GND I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O
Pin Number 90 91 92 93 94 95 96 97 98 99 100
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function CLK, I/O I/O MODE VCC VCC NC NC NC SDI, I/O CLK, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O VCCA I/O VCCA I/O
CLKB, I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O
DCLK, I/O DCLK, I/O PRA, I/O PRA, I/O
CLKA, I/O CLKA, I/O
v5.0
87
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
160-Pin PQFP Package (Top View)
160 1
160-Pin PQFP
88
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
160- P in P Q FP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A42MX09 Function I/O DCLK, I/O NC I/O I/O NC I/O I/O I/O NC GND NC I/O I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O NC I/O I/O I/O NC I/O GND NC I/O I/O I/O NC I/O I/O SDI, I/O I/O GND
A42MX16 Function I/O DCLK, I/O I/O I/O I/O VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCI I/O I/O SDI, I/O I/O GND
A42MX24 Fucntion I/O DCLK, I/O I/O I/O (WD) I/O (WD) VCCI I/O I/O I/O I/O GND I/O I/O (WD) I/O (WD) I/O PRB, I/O I/O CLKB, I/O I/O VCCA CLKA, I/O I/O PRA, I/O I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) GND I/O (WD) I/O I/O I/O VCCI I/O (WD) I/O (WD) SDI, I/O I/O GND
Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
A42MX09 Function I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O NC I/O NC I/O I/O VCCA VCCI GND VCCA GND (LP) I/O I/O GND I/O I/O I/O I/O GND NC I/O I/O I/O I/O NC I/O NC I/O NC GND
A42MX16 Function I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA GND (LP) I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
A42MX24 Fucntion I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA GND (LP) TCK, I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
v5.0
89
40MX and 42MX FPGA Families
160- P in P Q FP (C ont inu ed)
Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
A42MX09 Function I/O SDO, I/O I/O I/O I/O NC I/O I/O GND NC I/O I/O I/O I/O I/O I/O I/O VCCA GND NC I/O I/O NC I/O I/O I/O I/O I/O GND NC I/O I/O I/O NC I/O NC I/O I/O I/O GND
A42MX16 Function I/O SDO, I/O I/O I/O I/O VCCI I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O GND
A42MX24 Fucntion I/O SDO, TDO, I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O (WD) GND I/O I/O I/O I/O I/O I/O I/O (WD) I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O GND I/O I/O (WD) I/O (WD) I/O VCCI I/O (WD) I/O (WD) I/O TDI, I/O TMS, I/O GND
Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
A42MX09 Function I/O I/O I/O NC GND I/O I/O I/O NC GND I/O I/O I/O I/O NC I/O I/O NC VCCI GND NC I/O I/O I/O GND NC I/O I/O I/O NC NC NC NC NC GND I/O I/O I/O MODE GND
A42MX16 Function I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O MODE GND
A42MX24 Fucntion I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O MODE GND
90
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
208-Pin PQFP Package (Top View)
208 1
208-Pin PQFP
v5.0
91
40MX and 42MX FPGA Families
208- P in P Q FP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A42MX16 Function GND NC MODE I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O NC VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O NC NC
A42MX24 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
A42MX36 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
A42MX16 Function NC I/O I/O I/O I/O I/O I/O NC NC GND GND I/O I/O I/O I/O I/O I/O VCCI NC NC I/O I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA NC I/O I/O I/O I/O
A42MX24 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O
A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O QCLKA, I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O GND VCCA VCCI I/O I/O I/O I/O
92
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
208- P in P Q FP (C ont inu ed)
Pin Number 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
A42MX16 Function I/O I/O I/O I/O NC NC I/O I/O I/O I/O NC NC NC VCCI I/O I/O I/O I/O SDO, I/O I/O GND NC I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
A42MX24 Function I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
A42MX36 Function I/O (WD) I/O (WD) I/O I/O I/O I/O QCLKB, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
Pin Number 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
A42MX16 Function I/O I/O GND (LP) VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O I/O I/O NC NC NC NC GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O I/O I/O VCCI NC NC I/O I/O
A42MX24 Function I/O TCK, I/O GND (LP) VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD)
A42MX36 Function I/O TCK, I/O GND (LP) VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O SDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD)
SDO, TDO, I/O SDO, TDO, I/O
v5.0
93
40MX and 42MX FPGA Families
208- P in P Q FP (C ont inu ed)
Pin Number 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188
A42MX16 Function I/O I/O NC I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O NC NC VCCA GND I/O CLKB, I/O I/O PRB, I/O
A42MX24 Function I/O (WD) I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O
A42MX36 Function I/O (WD) I/O QCLKD, I/O I/O I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O I/O VCCI VCCA GND I/O CLKB, I/O I/O PRB, I/O
Pin Number 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
A42MX16 Function I/O I/O I/O I/O NC NC NC I/O NC NC I/O I/O NC VCCI I/O I/O I/O I/O DCLK, I/O I/O
A42MX24 Function I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O VCCI I/O (WD) I/O (WD) I/O I/O DCLK, I/O I/O
A42MX36 Function I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) QCLKC, I/O I/O I/O I/O I/O I/O VCCI I/O (WD) I/O (WD) I/O I/O DCLK, I/O I/O
94
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
240-Pin PQFP Package (Top View)
240 1
* * *
* * *
240-Pin PQFP
* * *
v5.0
* * *
95
40MX and 42MX FPGA Families
240- P in P Q FP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A42MX36 Function I/O DCLK, I/O I/O I/O I/O I/O (WD) I/O (WD) VCCI I/O I/O I/O I/O I/O I/O QCLKC, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O PRB, I/O I/O CLKB, I/O I/O GND VCCA VCCI I/O CLKA, I/O I/O PRA, I/O I/O I/O I/O (WD) I/O (WD) I/O I/O
Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
A42MX36 Function I/O I/O I/O I/O QCLKD, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O SDI, I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
A42MX36 Function I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI VCCA GND (LP) TCK, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND
Pin Number 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
A42MX36 Function GND I/O SDO, TDO, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD) I/O (WD) I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O VCCI VCCA GND I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD)
96
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
240- P in P Q FP (C ont inu ed)
Pin Number 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
A42MX36 Function I/O I/O I/O (WD) I/O (WD) I/O QCLKA, I/O I/O I/O I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O I/O TDI, I/O TMS, I/O GND
Pin Number 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
A42MX36 Function VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220
A42MX36 Function I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O
Pin Number 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
A42MX36 Function I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O GND MODE VCCA GND
v5.0
97
40MX and 42MX FPGA Families
Package Pin Assignments (continued) 80-Pin VQFP
1
80
80-Pin VQFP
98
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
80- Pi n VQFP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A40MX02 Function I/O NC NC NC I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O NC NC NC VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O
A40MX04 Function I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O
Pin Number 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
A40MX02 Function NC NC NC I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O
A40MX04 Function I/O I/O I/O I/O I/O I/O GND I/O I/O CLK, I/O I/O MODE VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O
v5.0
99
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
100- P in VQF P P ackag e (T op V iew )
100 1
100-Pin VQFP
100
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
100-Pin VQFP Package
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A42MX09 Function I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O
A42MX16 Function I/O MODE I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O NC VCCI I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O SDO, I/O
Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
A42MX09 Function I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND (LP) VCCA VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O DCLK, I/O
A42MX16 Function I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND (LP) VCCA VCCI VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O GND I/O I/O PRA, I/O I/O CLKA, I/O VCCA I/O CLKB, I/O I/O PRB, I/O I/O GND I/O I/O I/O I/O I/O DCLK, I/O
v5.0
101
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
176-Pin TQFP Package (Top View)
176 1
176-Pin TQFP
102
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
176- P in T Q FP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A42MX09 Function GND MODE I/O I/O I/O I/O I/O NC I/O NC NC I/O NC I/O I/O I/O I/O GND NC NC I/O NC GND NC VCCA NC NC VCCI NC I/O I/O I/O NC I/O I/O I/O NC NC I/O I/O I/O I/O I/O I/O
A42MX16 Function GND MODE I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O
A42MX24 Function GND MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
A42MX09 Function GND I/O I/O I/O I/O I/O I/O NC I/O NC NC I/O NC I/O I/O I/O NC I/O I/O NC I/O NC GND VCCA I/O I/O I/O I/O I/O NC I/O I/O NC NC I/O NC I/O NC I/O I/O I/O NC SDO, I/O I/O
A42MX16 Function GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCI I/O I/O I/O I/O SDO, I/O I/O
A42MX24 Function GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O GND VCCA I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O SDO, TDO, I/O I/O
v5.0
103
40MX and 42MX FPGA Families
176- P in T Q FP (C ont inu ed)
Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
A42MX09 Function GND I/O I/O I/O I/O I/O I/O NC NC I/O I/O I/O NC I/O NC I/O I/O GND NC NC GND (LP) VCCA GND VCCI VCCA NC NC NC I/O I/O I/O I/O NC I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O
A42MX16 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O GND I/O I/O GND (LP) VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O
A42MX24 Function GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND (LP) VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
A42MX09 Function GND I/O SDI, I/O NC I/O I/O I/O NC I/O I/O NC NC NC I/O NC I/O I/O I/O NC PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O I/O PRB, I/O NC I/O I/O I/O NC NC I/O NC I/O NC I/O I/O NC I/O DCLK, I/O I/O
A42MX16 Function GND I/O SDI, I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCI I/O I/O I/O I/O DCLK, I/O I/O
A42MX24 Function GND I/O SDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O (WD) I/O (WD) I/O I/O DCLK, I/O I/O
104
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s
208-Pin CQFP (Top View)
208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157
Pin #1 Index
1 2 3 4 5 6 7 8
156 155 154 153 152 151 150 149
A42MX36 208-Pin CQFP
44 45 46 47 48 49 50 51 52 113 112 111 110 109 108 107 106 105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
v5.0
105
40MX and 42MX FPGA Families
208-Pin CQFP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A42MX36 Function GND VCCA MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O
Pin Number 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O QCLKA, I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O GND
Pin Number 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
A42MX36 Function VCCA VCCI I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O QCLKB, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O TDO, I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin Number 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
A42MX36 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND (LP) VCCA GND VCCI VCCA I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
106
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
208-Pin CQFP (Continued)
Pin Number 157 158 159 160 161 162 163 164 165 166 167 168 169
A42MX36 Function GND I/O SDI, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD) I/O (WD)
Pin Number 170 171 172 173 174 175 176 177 178 179 180 181 182
A42MX36 Function I/O QCLKD, I/O I/O I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O I/O VCCI
Pin Number 183 184 185 186 187 188 189 190 191 192 193 194 195
A42MX36 Function VCCA GND I/O CLKB, I/O I/O PRB, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD)
Pin Number 196 197 198 199 200 201 202 203 204 205 206 207 208
A42MX36 Function QCLKC, I/O I/O I/O I/O I/O I/O VCCI I/O (WD) I/O (WD) I/O I/O DCLK, I/O I/O
v5.0
107
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
256-Pin CQFP (Top View)
256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193
Pin #1 Index
1 2 3 4 5 6 7 8
192 191 190 189 188 187 186 185
A42MX36 256-Pin CQFP
56 57 58 59 60 61 62 63 64 137 136 135 134 133 132 131 130 129
65 66 67 68 69 70 71 72 73
121 122 123 124 125 126 127 128
108
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
256-Pin CQFP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A42MX36 Function NC GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND VCCA GND TCK, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O
Pin Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
A42MX36 Function I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND NC NC NC I/O SDO, TDO, I/O I/O I/O (WD) I/O (WD) I/O VCCI I/O I/O I/O I/O (WD) GND I/O, (WD) I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O
Pin Number 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129
A42MX36 Function I/O, (WD) I/O, (WD) I/O I/O I/O I/O I/O I/O VCCI VCCA GND GND I/O I/O I/O I/O I/O I/O I/O, (WD) I/O, (WD) I/O I/O I/O, (WD) I/O, (WD) I/O QCLKA, I/O I/O GND I/O I/O I/O I/O VCCI I/O I/O, (WD) I/O, (WD) I/O I/O I/O I/O GND NC NC
Pin Number 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172
A42MX36 Function NC GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O VCCA VCCI GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCCA I/O I/O
v5.0
109
40MX and 42MX FPGA Families
256-Pin CQFP (Continued)
Pin Number 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193
A42MX36 Function I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O MODE VCCA GND NC NC NC
Pin Number 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214
A42MX36 Function I/O DCLK, I/O I/O I/O I/O I/O (WD) I/O (WD) VCCI I/O I/O I/O I/O GND I/O I/O QCLKC, I/O I/O I/O (WD) I/O (WD) I/O I/O
Pin Number 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235
A42MX36 Function I/O (WD) I/O (WD) I/O PRB, I/O I/O CLKB, I/O I/O GND GND VCCA VCCI I/O CLKA, I/O I/O PRA, I/O I/O I/O I/O (WD) I/O (WD) I/O I/O
Pin Number 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256
A42MX36 Function I/O I/O I/O I/O QCLKD, I/O I/O I/O (WD) GND I/O (WD) I/O I/O I/O VCCI I/O I/O (WD) I/O (WD) I/O SDI, I/O I/O GND NC
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Pa c ka ge P i n A s si g nm e n t s (continued)
272- P in BGA P ack age (T op Vie w)
1 A B C D E F G H J K L M N P R T U V W Y 272-Pin PBGA 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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40MX and 42MX FPGA Families
272-Pin PBGA
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3
A42MX36 Function GND GND I/O I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O CLKA I/O I/O I/O I/O I/O (WD) I/O I/O GND GND GND GND DCLK, I/O I/O I/O I/O I/O (WD) I/O PRB, I/O I/O I/O I/O (WD) I/O I/O I/O (WD) I/O I/O (WD) I/O GND GND I/O MODE GND
Ball C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E17 E18
A42MX36 Function I/O I/O (WD) I/O QCLKC, I/O I/O I/O CLKB PRA, I/O I/O (WD) I/O QCLKD, I/O I/O I/O (WD) SDI, I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O VCCA I/O (WD) VCCI I/O VCCI I/O VCCI I/O VCCA GND I/O I/O I/O I/O I/O I/O VCCA VCCI I/O
Ball E19 E20 F1 F2 F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2 H3 H4 H17 H18 H19 H20 J1 J2 J3 J4 J9 J10 J11 J12 J17 J18 J19 J20 K1 K2 K3 K4 K9
A42MX36 Function I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O VCCI VCCI I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCA I/O I/O I/O I/O I/O I/O VCCI GND
Ball K10 K11 K12 K17 K18 K19 K20 L1 L2 L3 L4 L9 L10 L11 L12 L17 L18 L19 L20 M1 M2 M3 M4 M9 M10 M11 M12 M17 M18 M19 M20 N1 N2 N3 N4 N17 N18 N19 N20 P1 P2 P3 P4
A42MX36 Function GND GND GND I/O VCCA VCCA GND (LP) I/O I/O VCCA VCCA GND GND GND GND VCCI I/O I/O TCK, I/O I/O I/O I/O VCCI GND GND GND GND I/O I/O I/O I/O I/O I/O I/O VCCI VCCI I/O I/O I/O I/O I/O I/O VCCA
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272-Pin PBGA (Continued)
Ball P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1 T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5
A42MX36 Function I/O I/O I/O I/O I/O I/O I/O VCCI VCCI I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O VCCI
Ball U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10
A42MX36 Function I/O (WD) I/O I/O I/O (WD) VCCA VCCI I/O I/O QCLKB, I/O I/O VCCI I/O GND I/O I/O I/O I/O GND GND I/O I/O I/O I/O (WD) I/O I/O
Ball V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15
A42MX36 Function I/O I/O I/O (WD) I/O I/O (WD) I/O I/O SDO, TDO, I/O I/O I/O GND GND I/O TMS, I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O (WD) I/O I/O
Ball W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
A42MX36 Function I/O (WD) I/O I/O (WD) GND GND GND GND I/O TDI, I/O I/O (WD) I/O QCLKA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (WD) GND GND
v5.0
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40MX and 42MX FPGA Families
Li s t o f C ha ng e s
The following table lists critical changes that were made in the current version of the document.
Previous version v4.0.1 Changes in current version (v6.0) Page
Because the changes in this data sheet are extensive and technical in nature, this should ALL be viewed as a new document. Please read it as you would a data sheet that is published for the first time. Note that the "Package Characteristics and Mechanical Drawings" section has been eliminated from the data sheet. The mechanical drawings are now contained in a separate document, "Package Characteristics and Mechanical Drawings," available on the Actel web site.
D at a S he et Ca t e g o r i e s
In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. These data sheets are marked as "Advanced" or Preliminary" data sheets. The definition of these categories are as follows:
Adv anc ed
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
P rel im i nar y
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unm ar ked (pr odu ct ion)
The data sheet contains information that is considered to be final.
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Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44 (0)1256 305600 Fax: +44 (0)1256 355420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668
5172136-6/2.01

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